The Peak of the AI Memory Supercycle: 5 Decisive Moments for HBM That Will Shake the 2026 Semiconductor Market

• Introduction: AI Hitting the 'Memory Wall' — HBM Emerges as the Savior
  • Compute Power vs Memory Bandwidth: A 30-Year Divergence
  • The Arrival of the Trillion-Parameter Era
  • NVIDIA Vera Rubin: The First Major Consumer of HBM4
  • The Heart of the $1 Trillion Semiconductor Market
• [Takeaway 1] The Biggest Boom Since the 1990s: The Return of the 'Memory Supercycle'
  • Bank of America's Declaration: "The Biggest Boom Since the 1990s"
  • Memory Market Size Forecast: A Massive $440B Wave
  • Why a 'Supercycle': Comparison with the Past
  • Explosive Growth of the HBM Market
  • HBM3E Price Increases: Evidence of Supply-Demand Imbalance
  • Investment Implications: BofA's Top Pick
• [Takeaway 2] Breaking the 16-Layer (16-Hi) Barrier: The Magic of One-Third the Thickness of a Human Hair
  • CES 2026: SK Hynix Unveils 16-Hi HBM4
  • JEDEC 775um: An Immovable Wall
  • 30um Wafer Thinning: Extreme Precision
  • TSV (Through-Silicon Via): The Secret of the Vertical Highway
  • HBM4 JEDEC Standard Core Specs (JESD270-4)
  • MR-MUF: SK Hynix's Secret Weapon
    • MR-MUF vs TC-NCF Comparison
    • Why MR-MUF Is Maintained Even for 16-Hi
  • Hybrid Bonding: The Bonding Technology of the Future
• [Takeaway 3] The Era of 'Custom HBM (cHBM)': Memory Embraces Logic
  • The Shift from Standard HBM to Custom HBM
  • Base Die Transition to Logic Process
  • sHBM vs cHBM Detailed Comparison
  • Near-Memory Computing: A Paradigm Shift in Data Movement
  • The Future of Custom HBM: Beyond 2027
• [Takeaway 4] SK Hynix's Defense vs Samsung and Micron's Counterattack
  • The Three-Way Structure: Three Axes of the HBM War
  • SK Hynix: "The King of AI Memory"
    • SK Hynix's Core Competitive Advantages
  • Samsung Electronics: The "One-Stop Shop" Strategy
    • Samsung's Differentiation Strategy
  • Micron: "The Avengers of Technological Innovation"
    • Micron's Core Strategy
  • Comprehensive 3-Company Strategy Comparison
• [Takeaway 5] HBM vs GDDR: Why Doesn't My Gaming PC Have HBM?
  • "Why Don't We Use the World's Best Memory Everywhere?"
  • Cost: The Price of TSV and 3D Stacking
  • Architecture Comparison: Vertical vs Horizontal
  • Performance Comparison: Bandwidth vs Clock Speed
  • Bifurcation of Use Cases
• Comprehensive HBM Generation Comparison Table
• Technology Roadmap: The Future of HBM (2026-2030)
  • 2027: HBM4E - The Dawn of Hybrid Bonding
  • 2028-2029: HBM5 - A New Chapter of 2+ TB/s
  • Beyond 2030: The Arrival of Embedded Cooling
• Investment Implications: Opportunities and Risks in the Memory Supercycle
  • Key Beneficiary Analysis
  • Investment Themes by Value Chain
  • Risks to Watch for When Investing
• Conclusion: The Paradigm Shift Toward 'Memory-as-Compute'
  • HBM4: Not Just a Generational Update, But an Inflection Point
  • Memory-as-Compute: A New Computing Paradigm
  • Roadmap: The World After HBM5
  • Final Message: The Future of Semiconductors Is Determined by "Memory"
• References

Introduction: AI Hitting the 'Memory Wall' — HBM Emerges as the Savior

"The memory wall is the single greatest bottleneck in the history of computing." — Wm. A. Wulf & Sally A. McKee, "Hitting the Memory Wall" (1995)

In 1995, Professors Wulf and McKee at the University of Virginia warned that the gap between processor performance and memory bandwidth would threaten the future of computing. Thirty years later in 2026, this prophecy has become the most painful reality of the AI era.

Compute Power vs Memory Bandwidth: A 30-Year Divergence

Over the past 20 years, computing performance has improved approximately 10,000x, while memory bandwidth has only increased about 10x. According to TrendForce, peak FLOPS of server hardware scales by 3.0x every two years, while DRAM bandwidth scales by only 1.6x and interconnect bandwidth by a mere 1.4x. This structural imbalance means that AI workloads are inherently memory-bandwidth-limited workloads.

[Memory Wall Conceptual Diagram]

Performance
    ^
    |     ★ GPU Compute (FLOPS)
    |    /    ~3.0x / 2 years
    |   /
    |  /          ☆ Memory Bandwidth
    | /          /    ~1.6x / 2 years
    |/          /
    |----------/----------→ Time
    |         /
    |        /   ← This gap is the "Memory Wall"
    |       /
    |------/
    |
    +--------------------------------→ Year
    2000      2010      2020      2026

The Arrival of the Trillion-Parameter Era

As of 2026, AI model parameter counts have already surpassed the trillions. GPT-4 class models have over 1 trillion parameters, and next-generation models are racing toward 10 trillion parameters. Loading a single model into memory alone requires tens to hundreds of GB of HBM, and the training and inference processes must read and write this memory at speeds of several TB per second.

NVIDIA Vera Rubin: The First Major Consumer of HBM4

NVIDIA unveiled its next-generation AI platform Vera Rubin at CES 2026. The Rubin GPU, manufactured on TSMC's 3nm process, integrates 336 billion transistors and achieves 50 PFLOPS in NVFP4 inference. The key is memory. Each Rubin GPU features 8 HBM4 stacks, providing a total of 288GB capacity and approximately 13 TB/s or more of memory bandwidth. This represents roughly a 3x increase in memory bandwidth compared to Blackwell.

The Vera Rubin NVL72 rack system operates 72 Rubin GPUs and 36 Vera CPUs as a unified computing fabric, and the NVL144 full rack configuration boasts a staggering 20,736 TB of HBM4 memory.

The Heart of the $1 Trillion Semiconductor Market

In 2026, the global semiconductor market is virtually certain to surpass **$1 trillion (approximately$975B to $1T)** for the first time in history. According to Omdia's analysis, the computing and data storage segment will grow 41.4$500 billion. The SIA (Semiconductor Industry Association) officially forecasted $1 trillion for 2026, following$791.7 billion in revenue in 2025.

At the center of this massive market lies memory semiconductors, and among them, HBM (High Bandwidth Memory) has risen as a strategic chokepoint for AI infrastructure. SK Hynix and Micron have reported that their entire 2026 HBM production is already sold out, signifying that HBM has become not just a component but a scarce resource of the AI industry.

[Takeaway 1] The Biggest Boom Since the 1990s: The Return of the 'Memory Supercycle'

Bank of America's Declaration: "The Biggest Boom Since the 1990s"

Bank of America (BofA) has defined the 2026 memory semiconductor market as "the biggest supercycle since the 1990s." This is not simply a cyclical upturn, but a paradigm shift driven by structural demand changes in AI infrastructure investment.

"SK hynix is our global memory industry's Top Pick — the primary beneficiary of the AI-driven memory supercycle." — Bank of America, 2026 Semiconductor Outlook

Memory Market Size Forecast: A Massive $440B Wave

BofA forecasts the 2026 global memory semiconductor market will reach approximately $440B (440 billion dollars). The key indicators comprising this are as follows:

Why a 'Supercycle': Comparison with the Past

Memory semiconductors have traditionally been a cyclical industry with 3-4 year cycles. They repeatedly go through booms and busts, experiencing a severe downturn in 2023. However, this upswing cycle that began in 2024 is fundamentally different from the past:

1. Changed demand structure: Past memory demand depended on PCs and smartphones, but this time a massive new demand driver has emerged — AI data centers
2. Structural rise in ASP (Average Selling Price): AI-grade HBM maintains ASPs 5-10x higher than regular DRAM
3. Persistent supply constraints: HBM manufacturing requires 3-5x longer lead times and more complex processes than regular DRAM, making rapid supply expansion impossible
4. Major makers pivoting to HBM: SK Hynix, Samsung, and Micron are all concentrating production capacity on HBM, tightening the supply of commodity DRAM/NAND as well — a dual squeeze

Explosive Growth of the HBM Market

Looking at the HBM market alone, the growth trajectory is even more dramatic:

[HBM Market Size Trends and Forecast]

$54.6B ■■■■■■■■■■■■■■■■■■■■■■■■■■■ (+58%)
$34.5B ■■■■■■■■■■■■■■■■■■ (+280%)
 $9.1B ■■■■■
 $2.5B ■■
 $1.1B ■
------+------+------+------+------+------→
     2022   2023   2024   2025(E) 2026(E)

The HBM market, which was approximately $1.1B in 2022, is projected to reach$54.6B — growing roughly 50x in just four years. This represents approximately 12.4% of the total memory market, demonstrating that HBM as a single product category is driving the growth of the entire memory industry.

HBM3E Price Increases: Evidence of Supply-Demand Imbalance

Samsung Electronics and SK Hynix have reportedly raised HBM3E prices by approximately 20% for 2026 deliveries. This phenomenon is driven by explosive demand for AI accelerators exceeding supply. This demonstrates that memory semiconductors are no longer a commodity but are transitioning into premium strategic materials.

Investment Implications: BofA's Top Pick

BofA has selected SK Hynix as the Top Pick for the global memory industry. UBS predicts SK Hynix will capture approximately 70% market share in the HBM4 market for NVIDIA's Vera Rubin platform. However, some research firms also warn of potential price adjustments after 2026 due to intensifying competition and production capacity expansion, meaning investors should closely monitor the cycle peak timing.

[Takeaway 2] Breaking the 16-Layer (16-Hi) Barrier: The Magic of One-Third the Thickness of a Human Hair

CES 2026: SK Hynix Unveils 16-Hi HBM4

In January 2026, at CES 2026, SK Hynix unveiled the world's first 16-layer stacked (16-Hi) HBM4, shocking the industry. This product delivers 48GB or more capacity and over 2 TB/s bandwidth from a single stack. However, behind this achievement lies extreme engineering that challenges the limits of physics.

JEDEC 775um: An Immovable Wall

The height of an HBM stack is strictly limited to 775um (micrometers) by the JEDEC (Joint Electron Device Engineering Council) standard. This standard ensures compatibility with overall module height, thermal management, and substrate design when HBM stacks are placed on top of GPU packages.

Stacking 16 DRAM dies within 775um means that each die must be approximately 30um or thinner. For reference, a human hair is about 70-100um thick, so each individual DRAM die in HBM4 is roughly one-third the thickness of a human hair.

[HBM4 16-Hi Stack Structure Diagram]
                                            ← 775um (JEDEC standard height limit)
    ┌─────────────────────────────┐ ─┐
    │     Molding Compound        │  │
    ├─────────────────────────────┤  │
    │  DRAM Die #16  (~30um)      │  │
    ├─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┤  │
    │  Micro-bump / Bonding Layer │  │
    ├─────────────────────────────┤  │
    │  DRAM Die #15  (~30um)      │  │
    ├─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┤  │
    │  Micro-bump / Bonding Layer │  │
    ├─────────────────────────────┤  │
    │         ...                 │  │   16-layer DRAM
    │    (Die #14 ~ Die #3)       │  │   stacking
    │         ...                 │  │
    ├─────────────────────────────┤  │
    │  DRAM Die #2   (~30um)      │  │
    ├─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┤  │
    │  Micro-bump / Bonding Layer │  │
    ├─────────────────────────────┤  │
    │  DRAM Die #1   (~30um)      │  │
    ├─────────────────────────────┤ ─┘
    │                             │
    │    Base Die (Logic Die)     │ ← 5nm/4nm logic process
    │    - PHY, ECC, Control      │
    │                             │
    ├─────────────────────────────┤
    │   |||  |||  |||  |||  |||   │ ← TSV (Through-Silicon Via)
    │   |||  |||  |||  |||  |||   │   Thousands of vertical through-electrodes
    └─────────────────────────────┘
    ┌─────────────────────────────┐
    │      Silicon Interposer     │ ← 2.5D silicon interposer
    │  (substrate connecting GPU  │
    │   and HBM)                  │
    └─────────────────────────────┘

30um Wafer Thinning: Extreme Precision

In 12-Hi HBM3E, each die thickness was approximately 50um. For 16-Hi HBM4, this must be reduced to 30um. This difference is far more than simply "making it 20um thinner":

• Wafer warpage control: A 30um-thick silicon wafer bends as easily as paper. Flatness must be maintained at the micrometer scale
• TSV penetration precision: The aspect ratio of TSVs (Through-Silicon Vias) penetrating thinner dies changes, dramatically increasing the difficulty of etching and filling processes
• Die handling: 30um dies are extremely fragile, significantly increasing the risk of breakage during transport, alignment, and bonding
• Heat dissipation: More densely packed dies generate more heat, but the thermal dissipation paths between each die become narrower

TSV (Through-Silicon Via): The Secret of the Vertical Highway

TSV, the core technology of HBM, consists of electrodes that vertically penetrate each DRAM die. Data, clock, control signals, power, and ground all pass through these TSVs penetrating all 16 dies.

[TSV Structure Detail]

    Top DRAM Die
    ┌──────────────────┐
    │  ┌──┐ ┌──┐ ┌──┐ │   ← TSV holes filled with
    │  │Cu│ │Cu│ │Cu│ │      Cu (copper) pillars
    │  │  │ │  │ │  │ │      (diameter ~5-10um)
    │  │  │ │  │ │  │ │   ← Si (silicon) substrate (~30um thick)
    │  │  │ │  │ │  │ │
    │  └──┘ └──┘ └──┘ │
    ├──○──○──○──○──○──┤   ← Micro-bump (bonding junction)
    │  ┌──┐ ┌──┐ ┌──┐ │
    │  │Cu│ │Cu│ │Cu│ │
    │  │  │ │  │ │  │ │
    │  │  │ │  │ │  │ │   ← Precisely aligned with die below
    │  │  │ │  │ │  │ │
    │  └──┘ └──┘ └──┘ │
    └──────────────────┘
    Bottom DRAM Die

    * TSV diameter: ~5-10um
    * TSV pitch: ~40-55um
    * TSVs per die: thousands
    * Aspect Ratio: 3:1 ~ 6:1

HBM4's 2048-bit interface represents a data path that is 2x wider than HBM3's 1024-bit. This requires a significant increase in the number of TSVs, and the alignment precision between each TSV must be at the sub-micrometer (sub-um) level.

HBM4 JEDEC Standard Core Specs (JESD270-4)

JEDEC officially released the HBM4 standard (JESD270-4) on April 16, 2025. The key specifications are as follows:

The key design change is the separation of the command bus and data bus. Up through HBM3, command and data shared the same bus, but HBM4 separates them to increase concurrency and reduce latency. This is a design optimized for the pattern of reading and writing large amounts of data continuously during AI training.

MR-MUF: SK Hynix's Secret Weapon

The key weapon that enabled SK Hynix to dominate the HBM market is MR-MUF (Mass Reflow Molded Underfill) technology. This technology provides decisive advantages in thermal management and yield during the die stacking process.

MR-MUF vs TC-NCF Comparison

The key advantage of MR-MUF is bonding at room temperature with minimal force. In contrast, TC-NCF applies high temperatures of 300 degrees C and strong pressure, making die damage and warpage from thermal stress more likely.

SK Hynix secured a specialized epoxy molding compound (EMC) through an exclusive contract with Japan's Namics Corporation. This material enables more uniform gap filling and superior encapsulation, reducing voids, improving heat dissipation, and minimizing warpage.

Why MR-MUF Is Maintained Even for 16-Hi

SK Hynix has decided to maintain MR-MUF for 16-Hi HBM4 production. While next-generation fluxless bonding technology was also evaluated, they concluded it is still premature in terms of performance and cost. The maturity of MR-MUF technology and accumulated mass production know-how were deemed most advantageous for securing yield in 16-layer stacking.

Hybrid Bonding: The Bonding Technology of the Future

While MR-MUF remains viable up to 16-Hi, it is expected to reach physical limits at 20 layers or more. SK Hynix's VP of Packaging Development, Lee Kang-seok, has announced plans to introduce hybrid bonding technology starting with the HBM4E generation.

Hybrid bonding is a technology that directly bonds copper (Cu) pads without micro-bumps, enabling dramatic reduction in bonding pitch:

[Bonding Technology Evolution Roadmap]

         Micro-bump           Hybrid Bonding
      (Current MR-MUF)        (HBM4E/HBM5~)

    ┌─────────────┐         ┌─────────────┐
    │  DRAM Die   │         │  DRAM Die   │
    │             │         │             │
    └──○──○──○──┘         └──┤  ├──┤  ├──┘
       ↑  ↑  ↑               ↑  ↑  ↑  ↑
    Solder bump             Cu-Cu direct bonding
    (pitch ~40um)           (pitch ~10um or less)
    ┌──○──○──○──┐         ┌──┤  ├──┤  ├──┐
    │             │         │             │
    │  DRAM Die   │         │  DRAM Die   │
    └─────────────┘         └─────────────┘

    * Bump removal → reduced bonding height
    * Pitch reduction → increased TSV density possible
    * Reduced thermal resistance → improved heat dissipation

SK Hynix's P&T7 packaging factory under construction in Cheongju is planned as the facility for the first large-scale pilot application of hybrid bonding for 20-layer stacking variants.

[Takeaway 3] The Era of 'Custom HBM (cHBM)': Memory Embraces Logic

The Shift from Standard HBM to Custom HBM

What fundamentally distinguishes HBM4 from previous generations is the innovation in the base die. In the past, the HBM base die contained only simple I/O interfaces and basic control logic. However, starting with HBM4, the base die is evolving into a full-fledged logic chip.

Base Die Transition to Logic Process

As the base die process transitions from 12nm Planar to 5nm/4nm FinFET, the PHY (Physical Layer) circuit channel length has been dramatically reduced from 6mm to approximately 2mm. This simultaneously achieves reduced power consumption and lower latency through shorter signal transmission distances.

[Standard HBM vs Custom HBM Architecture Comparison]

  ┌──── Standard HBM (sHBM) ────┐    ┌──── Custom HBM (cHBM) ────┐
  │                              │    │                            │
  │  ┌─────────────────────┐    │    │  ┌─────────────────────┐  │
  │  │    DRAM Die Stack    │    │    │  │    DRAM Die Stack    │  │
  │  │   (8-Hi / 12-Hi)    │    │    │  │   (12-Hi / 16-Hi)   │  │
  │  └─────────────────────┘    │    │  └─────────────────────┘  │
  │  ┌─────────────────────┐    │    │  ┌─────────────────────┐  │
  │  │   Base Die (12nm)    │    │    │  │  Base Die (5nm/4nm)  │  │
  │  │                      │    │    │  │                      │  │
  │  │  ┌──────┐ ┌──────┐  │    │    │  │  ┌──────┐ ┌──────┐  │  │
  │  │  │ PHY  │ │ ECC  │  │    │    │  │  │ PHY  │ │ ECC  │  │  │
  │  │  └──────┘ └──────┘  │    │    │  │  └──────┘ └──────┘  │  │
  │  │                      │    │    │  │  ┌──────┐ ┌──────┐  │  │
  │  │  (Basic I/O only)    │    │    │  │  │Custom│ │Near- │  │  │
  │  │                      │    │    │  │  │Logic │ │Memory│  │  │
  │  │                      │    │    │  │  │(per  │ │Proc. │  │  │
  │  │                      │    │    │  │  │client│ │      │  │  │
  │  └─────────────────────┘    │    │  │  └──────┘ └──────┘  │  │
  │                              │    │  └─────────────────────┘  │
  └──────────────────────────────┘    └────────────────────────────┘

    * sHBM: Standardized I/O interface      * cHBM: Customer-specific logic integration
    * High versatility                      * Optimized linkage with GPU/ASIC
    * Relatively lower cost                 * Near-Memory Processing possible

sHBM vs cHBM Detailed Comparison

Near-Memory Computing: A Paradigm Shift in Data Movement

The most innovative concept in cHBM is Near-Memory Computing (also known as Near-Memory Processing, NMP). In current AI accelerator systems, the GPU reads data from HBM to fetch it to GPU cores for computation, then writes results back to HBM. This data movement process accounts for a significant portion of total power consumption.

In cHBM, some data preprocessing and memory management functions are performed directly in the base die inside the HBM stack. This enables:

1. Reduced GPU-to-memory data movement — energy savings
2. Reduced latency — less time the GPU spends waiting
3. Distributed computational load from GPU cores — improved overall system efficiency
4. Reduced data center power consumption — improved TCO (Total Cost of Ownership)

The Future of Custom HBM: Beyond 2027

Currently, cHBM is being developed through close co-design between NVIDIA and SK Hynix/Samsung. Starting in 2027, hyperscalers like Google, Amazon, and Microsoft are expected to directly commission custom HBM optimized for their proprietary AI chips (TPU, Trainium, Maia, etc.). This will mark the turning point where HBM evolves from a simple memory module into a customer-specific computing unit.

[Takeaway 4] SK Hynix's Defense vs Samsung and Micron's Counterattack

The Three-Way Structure: Three Axes of the HBM War

The 2026 HBM market features fierce competition among SK Hynix, Samsung Electronics, and Micron. Each company's strategy is fundamentally different, and these differences determine the market landscape.

[2026 HBM Market Share Forecast]

SK Hynix  ████████████████████████████████████████████████████  54%
Samsung   ████████████████████████████  28%
Micron    ██████████████████  18%

(Source: Comprehensive market analysis)

SK Hynix: "The King of AI Memory"

SK Hynix surpassed Samsung Electronics in annual operating profit for the first time in history in 2025, establishing itself as the memory champion of the AI era. As of January 2026, it reportedly secured approximately 70% of NVIDIA Vera Rubin platform HBM4 orders.

SK Hynix's Core Competitive Advantages

SK Hynix's P&T7 factory broke ground in April 2026, targeting full operation by late 2027. By integrating with the adjacent M15X production line, it will build a "Super-Fab" system that handles everything from DRAM wafer fabrication to 16-layer vertical stacking in one location.

Samsung Electronics: The "One-Stop Shop" Strategy

Samsung Electronics temporarily fell to third place in the HBM market in 2025, but launched a strong counterattack in 2026. Samsung's Semiconductor CEO Jeon Young-hyun stated that "customers have evaluated that 'Samsung is back.'"

Samsung's Differentiation Strategy

Samsung's "one-stop shop" strategy leverages the structural advantage of being the only company in the world that possesses advanced foundry (4nm), a memory business division, and advanced packaging facilities under a single corporate umbrella. This reduces supply chain risks and shortens the development cycle from base die design to final packaging.

Samsung announced in February 2026 that HBM4 passed NVIDIA's Rubin platform verification, claiming it shipped commercial HBM4 as an industry first. This is an important milestone in curbing SK Hynix's dominance.

Micron: "The Avengers of Technological Innovation"

Micron has the lowest HBM market share among the three companies but is rapidly catching up through technological differentiation.

Micron's Core Strategy

Micron's biggest differentiator is its EUV (Extreme Ultraviolet) lithography-based 1-gamma DRAM node. While SK Hynix and Samsung rely on DUV (Deep UV)-based multi-patterning, Micron aggressively adopts EUV to achieve higher density and performance.

Micron's 12-Hi HBM4 samples achieved 2.8 TB/s bandwidth and 11 Gbps pin speed, demonstrating performance exceeding the JEDEC standard. This corresponds to a transfer rate of approximately 7.85 GT/s on the 2048-bit interface.

Comprehensive 3-Company Strategy Comparison

[Takeaway 5] HBM vs GDDR: Why Doesn't My Gaming PC Have HBM?

"Why Don't We Use the World's Best Memory Everywhere?"

If HBM is such superior memory, why do our gaming graphics cards still use GDDR? To answer this question, we must understand the fundamental differences in cost structure, physical design, and use cases.

Cost: The Price of TSV and 3D Stacking

The reason HBM is 4-5x more expensive than GDDR is clear:

The price of a single HBM3E memory module could purchase enough GDDR7 memory for roughly 10 graphics cards. The difference in GDDR7 cost in an RTX 5090 versus HBM3 cost in an H100 is tens of times greater.

Architecture Comparison: Vertical vs Horizontal

[HBM vs GDDR Physical Structure Comparison]

      ┌── HBM ──┐              ┌── GDDR ──┐

      ┌────────┐                 ┌───┐ ┌───┐ ┌───┐ ┌───┐
      │Stack 16│                 │   │ │   │ │   │ │   │
      │Stack 15│                 │ G │ │ G │ │ G │ │ G │
      │  ...   │                 │ D │ │ D │ │ D │ │ D │
      │Stack 2 │                 │ D │ │ D │ │ D │ │ D │
      │Stack 1 │                 │ R │ │ R │ │ R │ │ R │
      │Base Die│                 │   │ │   │ │   │ │   │
      └───┬────┘                 └─┬─┘ └─┬─┘ └─┬─┘ └─┬─┘
          │                        │     │     │     │
    ┌─────┴─────┐              ┌───┴─────┴─────┴─────┴───┐
    │ Interposer │              │         PCB               │
    └─────┬─────┘              │                           │
          │                     │    ┌────────────┐        │
    ┌─────┴─────┐              │    │    GPU     │        │
    │    GPU     │              │    │            │        │
    └───────────┘              │    └────────────┘        │
                                └───────────────────────────┘

    * HBM: Right next to GPU, on interposer   * GDDR: Around GPU, distributed on PCB
    * Ultra-wide (2048-bit) + short distance   * High clock (32-36 Gbps) + long distance
    * Low power, high bandwidth                * Relatively higher power, high clock speed

Performance Comparison: Bandwidth vs Clock Speed

Bifurcation of Use Cases

In conclusion, HBM and GDDR are the same "memory" but designed for completely different markets:

HBM's Domain: AI Data Centers / HPC

• Training ultra-large AI models: Hundreds of GB of model parameters resident in memory
• Large-scale inference: Processing thousands of simultaneous requests
• Core value: Bandwidth + Capacity + Power Efficiency
• Cost tolerance: GPU costs $30,000-$40,000 each — thousands of dollars in memory cost is acceptable

GDDR's Domain: Gaming / Consumer GPUs / Edge Inference

• Real-time rendering: Reading and writing frame buffers at high speed
• Consumer price range: GPU is $500-$2,000 — memory cost must stay within a few hundred dollars
• Core value: High clock speed + Low cost + Versatility
• Edge AI: GDDR is more cost-effective for inference with smaller models

[Memory Positioning by Use Case]

         Cost ↑
              │
              │  GDDR7
              │  ● Gaming GPUs
              │  ● Consumer electronics
              │  ● Edge inference
              │
              │─────────────────── Cost efficiency boundary
              │
              │  HBM4
              │  ● AI training/inference
              │  ● Data centers
              │  ● HPC/scientific computing
              │  ● LLM serving
              │
              └────────────────────→ Bandwidth requirement
            Low                    High

This bifurcation structure is likely to persist going forward. However, with the emergence of new standards like SPHBM4 (Standard Package HBM4), HBM variants mountable on standard organic substrates could emerge to target the mid-market of edge AI servers. JEDEC is currently developing the SPHBM4 standard, aiming to deliver HBM4-level performance in a reduced pin count package.

Comprehensive HBM Generation Comparison Table

Here is a summary of HBM technology evolution at a glance:

[HBM Bandwidth Evolution by Generation]

Bandwidth (GB/s per stack)
    ^
2000│                                          ████ HBM4
    │                                          ████
1500│                                          ████
    │                                   ████   ████
1200│                                   ████   ████
    │                                   ████   ████ HBM3E
 800│                            ████   ████   ████
    │                            ████   ████   ████ HBM3
 460│                     ████   ████   ████   ████
    │                     ████   ████   ████   ████ HBM2E
 256│              ████   ████   ████   ████   ████
    │              ████   ████   ████   ████   ████ HBM2
 128│       ████   ████   ████   ████   ████   ████
    │       ████   ████   ████   ████   ████   ████ HBM
    └───────┴──────┴──────┴──────┴──────┴──────┴────→
          2013   2016   2020   2022   2024   2026

A notable point is that HBM4's per-pin speed (6.4-8.0 Gbps) is actually lower than or similar to HBM3E (8.0-9.2 Gbps). This is because HBM4 adopted the strategy of doubling the interface width (1024 to 2048-bit) instead of increasing clock speed. Running a wider bus at lower clocks greatly improves power efficiency and makes it easier to ensure signal integrity.

Technology Roadmap: The Future of HBM (2026-2030)

[HBM Technology Roadmap Timeline]

2026         2027          2028          2029          2030
  │           │             │             │             │
  ▼           ▼             ▼             ▼             ▼
┌─────┐   ┌──────┐     ┌──────┐     ┌──────┐     ┌──────┐
│HBM4 │   │HBM4E │     │ HBM5 │     │HBM5E │     │ HBM6 │
│     │   │      │     │      │     │      │     │      │
│16-Hi│   │16-20 │     │20-Hi │     │20-24 │     │24+Hi │
│     │   │ Hi   │     │      │     │ Hi   │     │      │
│2TB/s│   │2+TB/s│     │2+TB/s│     │3+TB/s│     │4+TB/s│
│     │   │      │     │      │     │      │     │      │
│MR-  │   │Hybrid│     │Hybrid│     │Hybrid│     │Embedd│
│MUF  │   │Bond  │     │Bond  │     │Bond  │     │Cool  │
│     │   │Intro │     │Full  │     │Mature│     │Intro?│
└─────┘   └──────┘     └──────┘     └──────┘     └──────┘
  │           │             │             │             │
  ├── TSMC 3nm ──┤          │             │             │
  │           ├── TSMC 2nm ──────┤        │             │
  │           │             ├── TSMC A16 ──────┤        │
  │           │             │             ├── TSMC 1.4nm─┤
  │           │             │             │             │
  ├─ NVIDIA Rubin ──┤       │             │             │
  │           ├─ Feynman(?) ─────┤        │             │

2027: HBM4E - The Dawn of Hybrid Bonding

HBM4E targets mass production in the second half of 2027, with up to 20-layer stacking and 96-120 GB capacity expected. The key technology change is the full-scale introduction of hybrid bonding. By eliminating micro-bumps and switching to Cu-Cu direct bonding:

• TSV pitch can be further reduced for improved I/O density
• Reduced bonding height enables compliance with the 775um height limit even at 20 layers
• Reduced thermal resistance for improved heat dissipation

2028-2029: HBM5 - A New Chapter of 2+ TB/s

HBM5 is expected to fully adopt Wafer-to-Wafer (W2W) hybrid bonding. With 20-Hi stacking, it is projected to deliver over 2 TB/s bandwidth per stack and 96-120 GB capacity. Power per stack will increase to approximately 120W, requiring innovative thermal management technologies.

Beyond 2030: The Arrival of Embedded Cooling

Further in the future, technology to embed micro-channel cooling inside HBM stacks is being researched. This approach forms microscopic coolant fluid channels between DRAM dies, removing heat directly from inside the stack. This is expected to enable stacking beyond 24 layers while solving thermal challenges.

Investment Implications: Opportunities and Risks in the Memory Supercycle

Key Beneficiary Analysis

Investment Themes by Value Chain

[HBM Value Chain Investment Map]

[Design/IP]                    [Manufacturing]               [Packaging/Testing]
  │                              │                              │
  ├── Rambus (PHY IP)            ├── SK Hynix (DRAM)            ├── SK Hynix (MR-MUF)
  ├── Synopsys (EDA)             ├── Samsung (DRAM)             ├── Samsung (TC-NCF)
  ├── Cadence (EDA)              ├── Micron (DRAM)              ├── TSMC (CoWoS)
  │                              │                              ├── ASE/SPIL
  │                              │                              │
[Equipment/Materials]           [GPU/ASIC Customers]           [End Consumers]
  │                              │                              │
  ├── ASML (EUV litho)           ├── NVIDIA (Rubin)             ├── Microsoft (Azure)
  ├── Tokyo Electron (CVD)       ├── AMD (MI400)                ├── Google (TPU)
  ├── Hanmi Semi (TC Bonder)     ├── Intel (Falcon Shores)      ├── Amazon (Trainium)
  ├── Namics (EMC material)      ├── Broadcom (custom)          ├── Meta (MTIA)
  ├── BESI (Hybrid Bonder)       │                              │

Risks to Watch for When Investing

1. Cycle peak risk: As BofA calls it "the biggest supercycle since the 1990s," the possibility of a decline after the peak exists. Some analysts warn that price adjustments could come after 2026 due to intensifying competition and capacity expansion
2. Technology transition risk: Potential inventory adjustments during the transition from HBM4 to HBM4E
3. Geopolitical risk: US-China tech conflict, Taiwan risk (TSMC), Korean semiconductor export regulations, etc.
4. Demand volatility: Changes in AI investment cycles, potential hyperscaler Capex reductions
5. Technological alternatives: Emergence of technologies like CXL (Compute Express Link) memory and Processing-in-Memory (PIM) that could replace or complement HBM

Conclusion: The Paradigm Shift Toward 'Memory-as-Compute'

HBM4: Not Just a Generational Update, But an Inflection Point

HBM4 in 2026 is not simply "the next version after HBM3E." The 2x expansion of interface width, the transition of the base die to a logic process, and the emergence of custom HBM represent an inflection point where the fundamental role of memory is changing.

In the past, memory was a passive storage device that handed over data when the CPU/GPU requested it. However, HBM4's logic base die, Near-Memory Computing, and cHBM's custom logic integration show that memory is evolving into an active compute participant.

Memory-as-Compute: A New Computing Paradigm

[The Computing Paradigm Shift]

   Past (CPU-centric)            Present (GPU + HBM)          Future (Memory-as-Compute)
  ┌──────────────┐           ┌──────────────┐           ┌──────────────┐
  │     CPU      │           │     GPU      │           │  GPU + cHBM  │
  │  (Compute-   │           │  (Parallel   │           │  (Unified    │
  │   centric)   │           │   compute)   │           │   compute)   │
  │  ┌────────┐  │           │  ┌────────┐  │           │  ┌────────┐  │
  │  │Compute │←─┼──slow──→  │  │Compute │←─┼──fast──→  │  │Compute │  │
  │  └────────┘  │  bus      │  └────────┘  │  bus      │  └───┬────┘  │
  └──────────────┘           └──────────────┘           │     │       │
         ↕                          ↕                    │  ┌──┴───┐  │
      Slow memory                HBM (ultra-fast)        │  │NMP   │  │
  ┌──────────────┐           ┌──────────────┐           │  │Logic │  │
  │    DRAM      │           │  HBM3/HBM4   │           │  └──┬───┘  │
  │  (Passive    │           │ (High-speed   │           │     │      │
  │   storage)   │           │  storage)     │           │  ┌──┴───┐  │
  └──────────────┘           └──────────────┘           │  │Memory│  │
                                                         │  │Array │  │
         Data movement is        Data movement is        │  └──────┘  │
         the biggest             significantly           └──────────────┘
         bottleneck              improved                 Data movement minimized
                                                          + in-memory computation

In this paradigm, memory no longer just "stores." By performing computation where the data resides, it seeks to overcome the fundamental limitation of von Neumann architecture — the "cost of data movement."

Roadmap: The World After HBM5

Final Message: The Future of Semiconductors Is Determined by "Memory"

The "memory wall" that Professor Wulf warned about in 1995 is, thirty years later, meeting the greatest-ever computing demand in AI and fundamentally reshaping the landscape of the industry. In the past, the core question of the semiconductor industry was "how fast a processor can we build?" But the question of 2026 is this:

"How fast and how much data can we feed to the processor?"

The answer to this question is HBM, and SK Hynix, Samsung Electronics, and Micron are competing with trillions of won in investment and technology over this answer. HBM4 is the front line of that competition and a historic turning point where memory ascends from a mere component to a strategic core asset of the AI era.

References

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