필사 모드: AI Hardware EDA & Chip Design 2026 Complete Guide — Cadence Cerebrus + JedAI · Synopsys DSO.ai + AgentEngineer · Siemens Calibre AI · ANSYS PathFinder · NVIDIA ChipNeMo · Google AlphaChip · OpenROAD Deep Dive

Prologue — The Year Chip Design Exceeded Human Limits

In May 2026, the global semiconductor industry crosses five inflection points at the same time. TSMC N2 (2nm GAA) is in volume production. Samsung Foundry SF2 has ramped its yield. Intel 18A is shipping Panther Lake and Clearwater Forest. Japan's Rapidus started 2nm trial production at its Chitose IIM-1 fab in Hokkaido under license from IBM. NVIDIA crossed 3 trillion USD market cap, and Broadcom's ASIC business — running Google TPU, Meta MTIA, and ByteDance chips in parallel — passed 10 billion USD a quarter.

The problem is that every one of these nodes packs 10 billion or more transistors onto a single die. A P&R (Place and Route) task that 7-8 engineers finished in a year at 5nm now takes 30 engineers over two years at 2nm. EUV mask design, multi-patterning, GAA channel modeling, backside power delivery (BSPDN), and 3D-IC stacking all arrived at once.

So Cadence, Synopsys, and Siemens have embedded AI options across every one of their flagship tools. "AI EDA" — first commercialized by Synopsys DSO.ai in 2020 — became an industry standard six years later. This article walks the entire landscape end to end.

- **Commercial Big Three** — Cadence Cerebrus + JedAI, Synopsys DSO.ai + AgentEngineer, Siemens Calibre AI

- **Sign-off AI** — ANSYS PathFinder, RedHawk-SC, Calibre DRC/LVS

- **LLM for chip** — NVIDIA ChipNeMo, Synopsys Copilot, Cadence Joint Chip Copilot

- **DeepMind / academia** — Google AlphaChip, MIT Tiny Tapeout, Stanford OpenROAD

- **Open source** — OpenROAD, OpenLane 2, KLayout, OpenSTA

- **Korea / Japan** — Samsung SAFE AI, SK Hynix HBM AI, Rapidus 2nm, Renesas R-Car AI

- **Emerging ASICs** — Etched Sohu, MatX, Tenstorrent, Astera Labs, Cerebras WSE-3

We walk each tool's pricing, real-world measurements, limits, and 2026 deployment evidence in order.

Chapter 1 · Why AI EDA Became Mandatory in 2026

Demand first, technology second. Four axes of the 2026 chip design crisis.

- **Node complexity explosion** — Roughly 10,000 design rules at 5nm, 15,000 at 3nm, more than 20,000 at 2nm GAA. No human memorizes them all.

- **Senior engineer shortage** — Per IEEE / IEDM data, the global supply of senior digital designers (15+ years experience) sits at 60 % of the 2010 level. Retirements and career switches both spiked.

- **Tapeout cost explosion** — A 2nm mask set runs over 100 million USD. One bad tapeout shakes a company.

- **The hyperscaler ASIC war** — Google TPU v7, Meta MTIA 3, Amazon Trainium 3, Microsoft Maia 200 all hit volume in the same quarter. EDA tool throughput is the bottleneck.

AI was the only candidate that could attack all four at once, and the result exploded in the 2025-2026 window.

[Chip design flow, 5 stages — 2026 model]

1. Spec & architecture — RTL design, SystemVerilog, HLS

2. Synthesis & P&R — Gate-level synthesis, Place and Route (Cerebrus, DSO.ai)

3. Verification — UVM, formal, simulation (Verisium, VSO.ai)

4. Sign-off — STA, DRC/LVS, ESD, IR drop (Calibre, PathFinder)

5. Production & DFT — Test patterns, automatic defect diagnosis (Tessent, TSO.ai)

AI now reaches every stage, but stages 2-3-4 are where the largest economic value lives.

Chapter 2 · Cadence Cerebrus — RL-Driven Chip Design Explorer

**Cadence Cerebrus Intelligent Chip Explorer** (the Cerebrus page on cadence.com) launched in September 2021. Feed it RTL, and it orchestrates Innovus (P&R), Genus (synthesis), and Tempus (STA) automatically while a reinforcement-learning agent searches for the best PPA (Power, Performance, Area).

- **Launch** — September 2021, Cadence CDNS Live.

- **How** — An RL agent tunes thousands of synthesis and P&R parameters simultaneously.

- **Benchmarks** — Cadence reports 10-20 % PPA improvement and a third of the time vs. a human engineer.

- **In production** — Samsung Foundry, Renesas, and NXP have been disclosed as published case studies.

The idea originated in academic RL research (notably Google's AlphaChip Nature paper, 2020), but Cadence was first to commercialize it. Synthesis and P&R parameter combinations that a human spends days trying are now searched automatically.

Limits are real.

- **Black box** — RL cannot easily explain why it picked that combination.

- **License cost** — An option layered on Cadence Innovus; the exact price is under NDA. Industry estimates put it above 1 million USD a year.

- **Data hungry** — More in-house historical designs make the model converge better.

By 2026, Cerebrus is integrated with Cadence's Joint Enterprise Data + AI platform JedAI and learns from internal IP, block libraries, and past designs.

Chapter 3 · Cadence JedAI Platform — Unifying In-House EDA Data

**JedAI** (Joint Enterprise Data and AI Platform) is the data-and-learning platform Cadence announced in 2023. Inside one company, when multiple chip projects run in parallel, JedAI aggregates the data and reuses it across all the tools.

- **Data sources** — Synthesis logs, P&R results, verification logs, DFT patterns, sign-off results.

- **Connected tools** — Cerebrus, Verisium (verification), Allegro X (PCB), Optimality (verification), Joules (RTL Power).

- **Customer-data protection** — Training stays inside one customer; no cross-tenant sharing.

JedAI's core proposition is "a block that worked once is reused automatically on the next chip." Where IP reuse used to live in engineers' heads, the platform now recommends.

Chapter 4 · Cadence Verisium AI — Verification Automation

**Verisium AI** (released 2022) is Cadence's AI tool for the verification step. Inside a UVM (Universal Verification Methodology) testbench, an ML model learns which scenarios to run first.

- **Regression prioritization** — Past bugs drive the regression order.

- **Bug classification** — Failed tests are matched to RTL change history to triage debug.

- **Throughput** — More scenarios pass within the same time budget.

By 2026, Verisium integrates with SystemVerilog, UVM, cocotb, and the Xcelium simulator. Direct competitors are Synopsys VSO.ai and Siemens Questa AI.

Chapter 5 · Synopsys DSO.ai — The First Commercial AI EDA (2020)

**Synopsys DSO.ai** (Design Space Optimization for AI) was announced on 12 March 2020. It holds the title of the industry's first commercial AI EDA tool.

- **Launch** — 12 March 2020, SNUG (Synopsys Users Group).

- **First public customer case** — Samsung Foundry, July 2021.

- **Cumulative tapeouts** — Over 300 by September 2024, an estimated 700 by May 2026.

- **PPA improvement** — Synopsys quotes an average of 15-30 %.

- **Awards** — Nominated for IEEE/ACM Lifetime Contribution.

DSO.ai sits on top of Fusion Compiler and IC Compiler II. An RL agent runs thousands of synthesis-and-P&R parameter combinations in parallel to find the best PPA.

As of May 2026, DSO.ai is the first member of the Synopsys.ai family. VSO.ai (verification), TSO.ai (test), and ASO.ai (analog) followed in turn.

Chapter 6 · Synopsys AgentEngineer — Agentic Chip Design (March 2025)

**AgentEngineer** (announced 18 March 2025) is the newest Synopsys flow. Where DSO.ai was an "RL optimizer," AgentEngineer is "a framework where Claude / GPT-style agents call chip-design tools."

- **Announcement** — 18 March 2025, Synopsys SNUG Silicon Valley.

- **Backbone** — Synopsys's own LLM, with optional GPT-4 or Claude.

- **Tool calls** — Fusion Compiler, IC Validator, PrimeTime, VC Formal driven by natural language.

- **Agent personas** — Synthesis Engineer, Verification Engineer, DFT Engineer separated as distinct agents.

The flow is the same shape as OpenAI ChatGPT Agents Mode or Anthropic Claude Code. What is different is the tool surface — chip-design EDA. First production references shipped at Synopsys customer conferences in 2026, though deeper data remains under NDA.

Chapter 7 · Synopsys VSO.ai · TSO.ai · ASO.ai

DSO.ai was the P&R optimizer; siblings grew up next to it.

- **VSO.ai** (Verification Space Optimization) — Announced 2022. Drives UVM / SystemVerilog regression prioritization.

- **TSO.ai** (Test Space Optimization) — DFT / ATPG pattern compression. 30-50 % shorter test time.

- **ASO.ai** (Analog Space Optimization) — Announced 2023. Automates analog circuit sizing; integrated with Custom Compiler.

- **Synopsys.ai Copilot** — December 2023. Natural-language EDA command composition. Autocompletes PrimeTime · Verdi · IC Compiler commands.

As of 2026, the Synopsys.ai family is four optimizers plus one Copilot.

Chapter 8 · Siemens EDA Calibre AI — Sign-Off DRC/LVS Goes AI

Siemens EDA (formerly Mentor Graphics) emerged in 2017 when Siemens acquired Mentor for 4.5 billion USD. Its crown jewel is **Calibre** — the industry's standard DRC (Design Rule Check) and LVS (Layout vs Schematic) sign-off tool.

- **Calibre nmPlatform** — 28 years of accumulated sign-off authority. Certified by TSMC, Samsung, GlobalFoundries, and Intel Foundry.

- **Calibre Machine Learning OPC** — ML applied to optical proximity correction (OPC). Mask simulation acceleration.

- **Calibre Vision AI** — Announced 2024. DRC debug explained in natural language by an LLM.

- **Solido** — Variation-aware simulation. Siemens acquired Solido Design Automation in 2017.

- **Tessent AI** — DFT (Design for Test) pattern compression via ML.

Calibre's sign-off times stretched once 2nm GAA arrived with its design-rule explosion. AI options shave 30-50 % off those times.

Chapter 9 · ANSYS PathFinder AI — ESD Verification Automation

**ANSYS PathFinder** (ansys.com) is the standard ESD (electrostatic discharge) simulation tool. AI options arrived in 2024.

- **PathFinder ESD** — ESD circuit verification, automatic protection-diode detection.

- **PathFinder AI** — Learns ESD-verification results for the same IP block, then applies them automatically on the next chip.

- **RedHawk-SC** — Power integrity, IR-drop analysis.

- **HFSS / SIwave** — Signal integrity (SI), PCB / package.

In January 2024 Synopsys announced a 35-billion-USD acquisition of ANSYS, which closed in August 2025. As of 2026, every ANSYS tool is on a Synopsys.ai integration roadmap.

Chapter 10 · NVIDIA ChipNeMo — A Chip-Design-Specific LLM (October 2023)

**ChipNeMo** (NVIDIA Research paper, 31 October 2023) is a domain-specialized LLM for chip design.

- **Base model** — A domain-adapted version of Llama 2 13B.

- **Training data** — Roughly 24 billion tokens of in-house NVIDIA RTL, in-house EDA scripts, and in-house design documents.

- **Three use cases** — Engineer chatbot, code-review assistant, EDA-script auto-generation.

- **Released?** — Weights remain private; only the paper and demos are public.

ChipNeMo demonstrated two conclusions.

- **Domain-adaptive pretraining** beats general LLMs for chip-specific tasks.

- **A small (13B) model**, trained well, matches a generic 70B model on chip-design work.

By 2026, a successor model was disclosed at NVIDIA's keynotes as actually used on H100, B100, and Rubin design. The model itself remains in-house only.

Chapter 11 · Google DeepMind AlphaChip — RL Placement Inside the TPU (Nature 2021/2024)

**AlphaChip** (originally Chip Placement RL, Nature June 2021, with a 2024 update) is an RL-based macro-placement algorithm.

- **June 2021 Nature** — Co-authored by Anna Goldie, Azalia Mirhoseini, Jeff Dean, and others. Used on TPU v4.

- **2024 Nature Addendum** — Applied to TPU v5 / v6, matching or beating hand-placed designs on PPA.

- **External release** — Part of the RL code is open-sourced as Circuit Training on GitHub.

Academic debate followed. In 2023 some researchers published a critique that Google's baselines were too weak; Google responded with the 2024 Nature Addendum.

By 2026, AlphaChip's influence has spread across the entire RL-optimizer category, including Cadence Cerebrus and Synopsys DSO.ai. One academic paper birthed an industry segment.

Chapter 12 · OpenROAD + AutoTuner — Open-Source Auto P&R

**OpenROAD** (theopenroadproject.org) is a product of the U.S. DARPA IDEA program. It launched in 2018 with the goal of "RTL-to-GDS in 24 hours, fully automated."

- **GitHub** — github.com/The-OpenROAD-Project, MIT license.

- **Flow** — Yosys (synthesis) → OpenROAD (P&R) → KLayout / Magic (layout) → OpenSTA (timing).

- **AutoTuner** — A Bayesian optimizer that auto-tunes synthesis and P&R parameters.

- **PDK support** — SkyWater 130nm, GlobalFoundries 180nm, ASAP 7nm, and other open PDKs.

OpenROAD does not match commercial-tool PPA — official benchmarks land around 70-80 % of commercial-flow quality. But it crashes the barrier to entry for students, researchers, and tiny startups to zero.

Chapter 13 · OpenLane 2 + Efabless — Open Source All the Way to Tape-Out

**OpenLane** (github.com/efabless/openlane) is an automated flow on top of OpenROAD. Efabless operated OpenLane and released OpenLane 2 in 2024.

- **OpenLane 1** — Tcl-based, the main releases from 2021 to 2023.

- **OpenLane 2** — Python-based, released in 2024. Modular and better at debugging.

- **Efabless shutdown** — Efabless wound down in March 2025, but the OpenLane 2 code remained open source.

- **Efabless's legacy** — chipIgnite and MPW (Multi Project Wafer) shuttles let students and tiny startups actually tape out chips.

OpenLane's spiritual successor is Tiny Tapeout (run by Matt Venn since 2024). For about 1,000 USD, a student can put their own chip on a 130nm shuttle.

Chapter 14 · Hyperscaler In-House ASICs

The largest 2026 trend is big tech building its own silicon.

- **Google TPU v7** — Successor to Trillium, volume production in Q1 2026. Placed by AlphaChip.

- **Apple Neural Engine** — 38 TOPS NPU on M5, 32 TOPS on A19.

- **Tesla Dojo D2** — Announced 2025, used for FSD training.

- **AWS Trainium 3** — Announced Q1 2026 for training.

- **AWS Inferentia 3** — Inference.

- **Meta MTIA 3** — Volume production 2026. Recommendation and ranking.

- **Microsoft Maia 200** — Announced 2026 for Azure GPT inference.

This trend is rewriting EDA's revenue mix. Synopsys and Cadence revenue from cloud operators — Google, Microsoft, Amazon, Meta — is climbing faster than from the traditional chip vendors like NVIDIA, Intel, and AMD.

Chapter 15 · Verification AI — Verisium · VSO.ai · Questa AI

Verification is 60-70 % of chip-design cost. Naturally it is one of the first places AI landed.

- **Cadence Verisium AI** — Regression prioritization and bug classification.

- **Synopsys VSO.ai** — Auto-closes simulation coverage.

- **Synopsys VC SpyGlass** — ML in RTL static analysis.

- **Siemens Questa AI** — Announced 2024. LLM-based UVM sequence generation.

- **Synopsys VC Formal** — Formal verification, automatic assertion generation.

By 2026, an ML option in your verification suite is table stakes. Hardly any company signs off without it.

Chapter 16 · IP & Cores — Arm · RISC-V · Imagination

Chips are not built from scratch — they are assembled by buying IP cores.

- **Arm Cortex-X5** — Announced 2025, the flagship mobile CPU core.

- **Arm Cortex-A720AE** — Automotive safety grade.

- **Arm Ethos-U85** — Micro NPU.

- **RISC-V** — SiFive, Andes, Codasip ship cores.

- **RISC-V Vector (V) extension** — SIMD for AI inference.

- **Imagination Tech BXT** — Mobile GPU with AI acceleration.

- **Ceva NPU** — Voice and image AI acceleration.

The IP market grew livelier after Arm's IPO in September 2023. Arm's market cap stood near 150 billion USD by May 2026.

Chapter 17 · HLS (High-Level Synthesis) + AI

HLS is the flow that compiles C++ or SystemC into RTL automatically.

- **Cadence Stratus HLS** — C++ to RTL.

- **Siemens Catapult HLS** — Catapult AI option added.

- **Bluespec** — BSV (Bluespec SystemVerilog) to RTL, popular in academia.

- **Mythril / XLS** — Google's open-source HLS effort.

The HLS-plus-AI promise is "write your ML model in Python, get an accelerator RTL for free." As of 2026 it works partially, but the PPA still trails hand-written RTL by 20-30 %.

Chapter 18 · Photonic / Quantum Chip Design AI

New computing paradigms need AI EDA too.

- **Synopsys OptoCompiler** — Silicon-photonics design tool, launched 2021.

- **Cadence Stride** — Photonic simulation and layout.

- **PsiQuantum / Quantinuum** — Quantum-chip design with their own toolchains.

- Academic experiments using OpenAI or Anthropic models to autogenerate quantum circuits are also in progress.

Photonic chips exploded in 2026 demand thanks to data-center optical interconnect. Startups like Ayar Labs, Lightmatter, and Celestial AI run their own EDA flows.

Chapter 19 · Korean Chip AI — Samsung · SK Hynix · Rebellions · FuriosaAI

Korea's memory and System-LSI AI adoption surfaced fast between 2024 and 2026.

- **Samsung Foundry SAFE AI** — Samsung Advanced Foundry Ecosystem with AI optimization options. Co-certified with DSO.ai and Cerebrus.

- **Samsung Electronics System LSI** — Exynos 2500 / 2600 NPU design used AI EDA.

- **SK Hynix HBM AI** — Optimization of TSV (Through Silicon Via) design in HBM3E and HBM4.

- **Rebellions** — Following ATOM (inference), the REBEL (training + inference) chip is in design. Series C closed 2025.

- **FuriosaAI** — Renegade (2024), with successor RNGD in volume production. In production by 2026.

- **PuzzleAI** — A chip-design AI startup based in Seoul.

- **KAIST / SNU / POSTECH** — Active OpenROAD-based academic research.

- **ETRI** — Korea's national open-chip flow.

Korea is strong in memory (Samsung, SK Hynix) and in NPUs (Rebellions, FuriosaAI), and AI-EDA case studies inside both groups multiplied.

Chapter 20 · Japanese Chip AI — Rapidus · Renesas · Sony · PEZY

Japan, having lost semiconductor leadership in the 1990s, is making its 30-year comeback bid.

- **Rapidus 2nm** — IIM-1 fab in Chitose, Hokkaido. Licensed from IBM. Trial production in 2025, with volume production targeted for 2027 (on schedule as of May 2026).

- **Rapidus + IBM** — Joint PDK and design kits with the IBM Albany research center.

- **Renesas R-Car** — Automotive SoC. R-Car X5 integrates an NPU.

- **Sony image sensors** — CMOS sensors for smartphones and automotive, with AI pixel post-processing.

- **PEZY Computing PEZY-SC** — Many-core supercomputer accelerator. Backed by Japan's NEDO.

- **TSMC Japan (JASM)** — A joint venture with Sony and Denso. Fab 1 in Kumamoto runs 22 / 28nm; Fab 2 preps for 7nm.

Rapidus is a Japanese national project receiving over 900 billion yen (about 6 billion USD) of government investment. The 2026 milestone is IBM-licensed 2nm trial production, deeply tied to IBM's EDA know-how.

Chapter 21 · Foundry + AI — TSMC · Intel Foundry · Samsung

AI has entered the foundries themselves.

- **TSMC FinFlex / Open Innovation Platform** — PDKs for N3, N2, A16 with AI options. Co-certified with Cadence and Synopsys.

- **TSMC 3D Fabric** — CoWoS / SoIC / InFO stacking design with AI options.

- **Intel Foundry Services 18A** — Co-certified with Synopsys and Cadence. PowerVia (backside power) has AI options.

- **Samsung Foundry SF2 GAA** — 2nm GAA in volume production from 2024. AI-EDA verification options included.

- **GlobalFoundries 22FDX+** — FD-SOI, used for automotive and industrial.

Foundries pre-certify the AI options inside their PDKs so customers spend less time onboarding a new node.

Chapter 22 · Emerging ASIC Startups — Etched · MatX · Tenstorrent · Astera Labs

New users of EDA tools are growing fast.

- **Astera Labs** — IPO in 2024. AI-memory interconnect (CXL, UALink, NVLink Fusion) IP.

- **Tenstorrent** — Led by Jim Keller. RISC-V-based AI accelerators. Series D 690 million USD in 2024.

- **Etched Sohu** — Transformer-only ASIC. 120 million USD funding in 2024, with volume in 2026.

- **MatX** — Founded by ex-OpenAI staff. Transformer inference acceleration.

- **Cerebras WSE-3** — Wafer-scale engine, 900,000 cores on a single die.

- **Groq LPU** — Inference-only chip. Series D in 2024.

- **SambaNova Suite** — RDU (Reconfigurable Dataflow Unit).

These startups all design on Cadence or Synopsys tooling. Non-traditional chip firms now account for an estimated 30 % of EDA revenue in 2026.

Chapter 23 · NVIDIA at 3T USD and Broadcom AI ASIC — The Market Map

Pulling back to industry structure.

- **NVIDIA** — Market cap 3.1 trillion USD in May 2026. Monopoly grip on data-center GPU through H100, B100, Rubin.

- **AMD MI400 / MI500** — Volume production 2026. The only visible NVIDIA challenger.

- **Intel Gaudi 3** — AI accelerator after the Habana acquisition.

- **Broadcom AI ASIC** — Design partner to Google TPU, Meta MTIA, ByteDance. Quarterly revenue passed 10 billion USD.

- **Marvell** — ASIC design partner for Amazon Trainium and Inferentia.

- **TSMC capex** — Above 40 billion USD a year in 2026.

Inside this market, the EDA big three (Cadence, Synopsys, Siemens) are the chokepoint that all traffic flows through. That is why their AI tools set the industry-wide pace.

Chapter 24 · Pricing — How Expensive Are EDA Tools

EDA pricing lives under NDA, but industry estimates exist.

- **Cadence Innovus + Cerebrus** — Above 1 million USD per year.

- **Synopsys Fusion Compiler + DSO.ai** — Above 1 million USD per year.

- **Siemens Calibre nmPlatform** — Above 800,000 USD per year.

- **ANSYS RedHawk-SC** — Around 500,000 USD per year.

- **OpenROAD / OpenLane** — Free, open source.

- **Tiny Tapeout shuttle** — About 1,000 USD for a 130nm chip.

A startup typically begins on OpenROAD, OpenLane, and Tiny Tapeout to learn, brings a first prototype on 130nm or 180nm, then moves to commercial EDA for volume production.

Chapter 25 · Limits — What AI EDA Cannot Do

The picture is not all rosy. Real limits.

- **Black box** — Hard to explain why an RL optimizer picked that PPA.

- **Data hungry** — Companies with little in-house history extract less value from AI tools.

- **Trust cost** — Volume production requires a senior engineer to validate AI output anyway.

- **Weak generalization** — A model trained on one node (say 5nm) does not transfer cleanly to another (2nm).

- **Verification overhead** — AI output must be re-verified, which can erase the human-time savings.

The 2026 truth is that AI EDA does not replace senior engineers — it multiplies their throughput.

Chapter 26 · Ethical and Legal — IP Training Consent and Export Controls

AI EDA collides with two regulatory questions.

- **IP training consent** — Who owns the RTL and design data JedAI or DSO.ai train on? It varies by license.

- **U.S. export controls** — The U.S. Commerce Department BIS restricts EDA exports to China. Synopsys and Cadence have applied for EDA export licenses since 2022.

- **Semiconductor EAR** — Some EDA tools below the 2nm node are on the restricted list.

- **Dual use** — AI EDA used in military chips triggers tighter export rules.

In the U.S.-China trade environment of 2026, this affects the industry at large. Chinese EDA companies (EmpyreanTech, Cellix, Semitronix) are racing to build their own tools.

Chapter 27 · Learning Roadmap — Junior Digital Designer

A 2026 study path for students and new hires.

- **Languages** — SystemVerilog, Verilog, C++.

- **Methodology** — UVM for verification, with Synopsys VCS, Cadence Xcelium, or Mentor Questa.

- **Synthesis** — Basic commands of Synopsys Design Compiler or Cadence Genus.

- **P&R** — Synopsys IC Compiler II or Cadence Innovus.

- **Sign-off** — PrimeTime (STA), Calibre (DRC / LVS).

- **Open-source practice** — OpenROAD, OpenLane 2, walking a 130nm shuttle flow end to end.

- **AI tools** — Read the DSO.ai, Cerebrus, and ChipNeMo papers; follow the demos.

- **Certifications** — IEEE Certified Software Development Professional; national chip-design certifications.

A 2026 junior must combine the standard RTL-to-P&R flow with Python automation and AI tool usage all at once.

Chapter 28 · Beyond 2026 — The Future of Chip Design

Trends for the next two or three years.

- **2nm volume production** — TSMC N2, Samsung SF2, Intel 18A, Rapidus 2nm all in production.

- **3D-IC standardization** — Cheaper CoWoS, SoIC, Foveros. Package EDA becomes central.

- **AlphaChip's successors** — RL combined with LLMs. Natural language to chip spec to P&R.

- **Agentic EDA** — Synopsys AgentEngineer, Cadence Joint Chip Copilot.

- **Photonic chips** — Demand exploded around data-center optical interconnect.

- **Quantum chip design** — Tools getting ready in 2026 for a 2030 production horizon.

- **National EDA** — China's EmpyreanTech and a Japanese homegrown EDA flow are growing fast.

The chip industry split into two streams in the late 2020s. One is the ultra-dense advanced-node stream led by NVIDIA and TSMC. The other is the democratized stream led by OpenROAD and Tiny Tapeout. AI EDA accelerates both.

Chapter 29 · FAQ

**Q. Can a brand-new engineer design a chip if they use AI EDA tools?**

A. Not solo. AI EDA is a throughput multiplier for senior engineers, not a replacement. As of 2026 every production chip passes through senior validation.

**Q. Can students learn a chip-design flow for free?**

A. Yes. OpenROAD, OpenLane 2, KLayout, and OpenSTA are all free. With Tiny Tapeout you can fabricate a real 130nm chip for about 1,000 USD.

**Q. Should I learn Cadence or Synopsys?**

A. Learning both helps, but companies have a primary house. Korea's Samsung Foundry leans Synopsys; NVIDIA in the U.S. leans Cadence; Rapidus in Japan is Synopsys-heavy because of the IBM flow.

**Q. Can an LLM like ChipNeMo write RTL directly?**

A. Partly. Inside NVIDIA's data it sits around 50-70 % accuracy. Production chips still require human verification.

**Q. What is different about 2nm GAA vs. 5nm?**

A. The transistor structure changed from FinFET to GAA (Gate-All-Around), design rules roughly doubled, and backside power delivery (BSPDN) was added. Porting an existing design requires retuning every EDA tool setting.

Chapter 30 · Conclusion

Chip design in 2026 stands on two simultaneous extremes. On one side, the ultra-dense advanced-node flow led by NVIDIA Rubin, Google TPU v7, and Rapidus 2nm. On the other, the democratized flow led by OpenROAD, Tiny Tapeout, and the Efabless legacy. The EDA big three — Cadence, Synopsys, Siemens — sit between them, embedding AI options across every tool in their portfolio.

Five takeaways.

- **Synopsys DSO.ai** was the industry's first commercial AI EDA in 2020. Cumulative tapeouts are estimated above 700 by 2026.

- **Cadence Cerebrus + JedAI** improves PPA by 10-30 % through RL plus in-house data learning.

- **Siemens Calibre and ANSYS PathFinder** brought AI into sign-off.

- **NVIDIA ChipNeMo** proved domain-adaptive LLMs work. A 13B model matches 70B generics on chip-design tasks.

- **Google AlphaChip's** RL placement actually shipped on TPU v5 / v6 — academia rewriting an industry.

If you are a student, start with OpenROAD and Tiny Tapeout. If you are a new engineer, master the Synopsys or Cadence standard flow alongside the AI options. If you are a senior, learn the agentic flow — AgentEngineer, Joint Chip Copilot. Chip design in 2026 is still a human craft, but a human craft done together with AI.

References

- Cadence Cerebrus Intelligent Chip Explorer official page — https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/cerebrus-intelligent-chip-explorer.html

- Cadence JedAI Platform announcement — https://www.cadence.com/en_US/home/company/newsroom/press-releases.html

- Cadence Verisium AI — https://www.cadence.com/en_US/home/tools/system-design-and-verification/verisium-ai-driven-verification.html

- Synopsys DSO.ai official page — https://www.synopsys.com/implementation-and-signoff/ml-ai-design/dso-ai.html

- Synopsys AgentEngineer announcement (2025 SNUG) — https://www.synopsys.com/blogs/chip-design/synopsys-agentengineer-ai-chip-design.html

- Synopsys.ai Copilot — https://www.synopsys.com/ai/synopsys-ai-copilot.html

- Siemens EDA Calibre — https://eda.sw.siemens.com/en-US/ic/calibre-design/

- Siemens Solido — https://eda.sw.siemens.com/en-US/ic/solido/

- ANSYS PathFinder ESD — https://www.ansys.com/products/semiconductors/ansys-pathfinder

- NVIDIA ChipNeMo paper (arXiv 2310.00688) — https://arxiv.org/abs/2310.00688

- NVIDIA Research ChipNeMo page — https://research.nvidia.com/publication/2023-10_chipnemo-domain-adapted-llms-chip-design

- Google AlphaChip 2021 Nature paper — https://www.nature.com/articles/s41586-021-03544-w

- Google AlphaChip 2024 Nature Addendum — https://www.nature.com/articles/s41586-024-08032-7

- Google Circuit Training (open-source code) — https://github.com/google-research/circuit_training

- OpenROAD project — https://theopenroadproject.org/

- OpenROAD GitHub — https://github.com/The-OpenROAD-Project

- OpenLane 2 GitHub — https://github.com/efabless/openlane2

- Tiny Tapeout project — https://tinytapeout.com/

- Arm official cores page — https://www.arm.com/products/silicon-ip-cpu

- RISC-V International — https://riscv.org/

- TSMC Open Innovation Platform — https://www.tsmc.com/english/dedicatedFoundry/services/open_innovation_platform

- Intel Foundry Services — https://www.intel.com/content/www/us/en/foundry/overview.html

- Samsung Foundry SAFE — https://semiconductor.samsung.com/foundry/safe/

- Rapidus official — https://www.rapidus.inc/en/

- Astera Labs official — https://www.asteralabs.com/

- Tenstorrent official — https://tenstorrent.com/

- Etched Sohu — https://www.etched.com/

- MatX official — https://matx.com/

- Cerebras WSE-3 — https://www.cerebras.net/

- Tiny Tapeout 1000 USD shuttle — https://tinytapeout.com/runs/

- IEEE DAC (Design Automation Conference) — https://www.dac.com/

- IEDM (International Electron Devices Meeting) — https://www.ieee-iedm.org/