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Semiconductor Physics & Devices Complete Guide: From Energy Bands to FinFET

For electronics and electrical engineering students, semiconductor physics is an essential foundation. This guide systematically covers everything from quantum mechanics basics to the latest GAA transistors.

1. Quantum Mechanics Fundamentals

To understand semiconductor behavior, we need the language of quantum mechanics, not classical mechanics.

Wave-Particle Duality

de Broglie proposed that particles also have wave properties. The wavelength of an electron is:

$$\lambda = \frac{h}{p} = \frac{h}{mv}$$

where $h$ is Planck's constant and $p$ is momentum. At the atomic scale, electrons behave like waves, so classical mechanics cannot describe electron behavior in semiconductors.

The Schrödinger Equation

The time-independent Schrödinger equation describes the energy states of electrons in semiconductors:

$$-\frac{\hbar^2}{2m}\nabla^2\psi + V\psi = E\psi$$

The square of the wavefunction $|\psi|^2$, the solution to this equation, represents the probability density of finding an electron at a specific location.

Energy Quantization

The energy of an electron inside an infinite potential well (quantum well) is discrete, not continuous:

$$E_n = \frac{n^2\pi^2\hbar^2}{2mL^2}, \quad n = 1, 2, 3, \ldots$$

This principle is the fundamental reason for energy band formation in semiconductors.

Pauli Exclusion Principle

No two electrons can occupy the same quantum state. As a result, when N atoms bond together, each energy level splits into N separate levels, ultimately forming **energy bands**.

2. Crystal Structure and Energy Bands

Silicon's Diamond Cubic Structure

Silicon (Si) has a diamond cubic structure. Each Si atom forms covalent bonds with 4 neighboring atoms, based on an FCC (face-centered cubic) lattice.

The lattice constant is $a = 5.43$ Å, and this periodic potential determines the energy band structure.

Energy Band Formation

When N atoms bond together, each discrete energy level splits into N closely spaced levels. When the number of atoms is very large (~$10^{23}$), these levels become effectively continuous **energy bands**.

- **Conduction Band**: Energy region where electrons can move freely

- **Valence Band**: Energy region of electrons participating in bonding

- **Energy Band Gap** $E_g$: Forbidden region between the two bands

Direct vs. Indirect Bandgap

| ------------- | ------------ | -------- | ---------------------- |

| Si | 1.12 | Indirect | CPU, Memory |

| Ge | 0.67 | Indirect | High-frequency devices |

| GaN | 3.4 | Direct | High-power LED |

| SiC | 2.86 | Indirect | Power devices |

In direct bandgap semiconductors (GaAs, GaN), photons are efficiently emitted during electron-hole recombination. Si, being indirect bandgap, has poor light emission efficiency and is unsuitable for LEDs.

Effective Mass

Electrons in a crystal experience a periodic potential and have an **effective mass** $m^*$ different from the free electron mass $m_0$:

$$m^* = \hbar^2 \left(\frac{d^2E}{dk^2}\right)^{-1}$$

In Si, the electron effective mass is $m_n^* \approx 0.26\,m_0$ and the hole effective mass is $m_p^* \approx 0.37\,m_0$.

3. Electrical Properties of Semiconductors

Intrinsic Semiconductor

In a pure semiconductor, electron concentration $n$ equals hole concentration $p$:

$$n = p = n_i$$

$n_i$ is the intrinsic carrier concentration, which depends strongly on temperature:

$$n_i = \sqrt{N_c N_v}\exp\left(-\frac{E_g}{2k_BT}\right)$$

For Si at room temperature (300 K), $n_i \approx 1.5 \times 10^{10}$ cm$^{-3}$.

Fermi-Dirac Distribution

The probability that an energy state $E$ is occupied by an electron:

$$f(E) = \frac{1}{1 + \exp\left(\frac{E - E_F}{k_BT}\right)}$$

$E_F$ is the **Fermi level**. In an intrinsic semiconductor, it is located near the middle of the bandgap.

Mass Action Law

At thermal equilibrium, regardless of doping:

$$n \cdot p = n_i^2$$

This relationship is a core tool in semiconductor analysis.

Conduction Mechanisms

**Drift**: Carrier motion driven by electric field $\mathcal{E}$:

$$J_{drift} = (qn\mu_n + qp\mu_p)\mathcal{E}$$

**Diffusion**: Carrier motion driven by concentration gradient:

$$J_{diff} = qD_n\frac{dn}{dx} - qD_p\frac{dp}{dx}$$

Einstein relation: $D = \mu k_BT/q$

4. Doping and Extrinsic Semiconductors

n-type Semiconductor: Donor Doping

Doping Si with Group V elements (phosphorus P, arsenic As, antimony Sb) introduces extra electrons that move into the conduction band.

When donor concentration $N_D \gg n_i$:

$$n \approx N_D, \quad p \approx \frac{n_i^2}{N_D}$$

The Fermi level shifts toward the conduction band: $E_F = E_i + k_BT\ln(N_D/n_i)$

p-type Semiconductor: Acceptor Doping

Doping with Group III elements (boron B, aluminum Al, gallium Ga) makes holes the majority carriers.

When acceptor concentration $N_A \gg n_i$:

$$p \approx N_A, \quad n \approx \frac{n_i^2}{N_A}$$

Python: Carrier Concentration Calculation

Silicon intrinsic carrier concentration (as function of temperature)

k_B = 8.617e-5 # eV/K

T = np.linspace(200, 600, 400) # K

E_g = 1.12 # eV (Si)

N_c = 2.8e19 # cm^-3 effective density of states

N_v = 1.04e19 # cm^-3

n_i = np.sqrt(N_c * N_v) * np.exp(-E_g / (2 * k_B * T))

n-type semiconductor (N_D = 1e17 cm^-3)

N_D = 1e17

n_n = N_D * np.ones_like(T)

p_n = n_i**2 / N_D

plt.figure(figsize=(10, 6))

plt.semilogy(T, n_i, 'k-', label='Intrinsic ni', linewidth=2)

plt.semilogy(T, n_n, 'b--', label='n-type: n (N_D=1e17)', linewidth=2)

plt.semilogy(T, p_n, 'r--', label='n-type: p (minority)', linewidth=2)

plt.xlabel('Temperature (K)')

plt.ylabel('Carrier Concentration (cm^-3)')

plt.title('Si Carrier Concentration vs Temperature')

plt.legend()

plt.grid(True, alpha=0.3)

plt.tight_layout()

plt.show()

5. p-n Junction

The heart of semiconductor devices. Every semiconductor device analysis builds upon the p-n junction.

Depletion Region Formation

When p-type and n-type semiconductor are brought into contact:

1. Concentration gradient causes electrons to diffuse n→p and holes to diffuse p→n

2. Ionized donors (+) and acceptors (-) remain, forming a **space charge region**

3. The resulting internal electric field blocks further diffusion → **thermal equilibrium**

Built-in Potential

$$V_{bi} = \frac{k_BT}{q}\ln\left(\frac{N_A N_D}{n_i^2}\right)$$

For Si with $N_A = N_D = 10^{17}$ cm$^{-3}$, $V_{bi} \approx 0.83$ V.

Depletion Width

$$W = x_n + x_p = \sqrt{\frac{2\varepsilon_s}{q}\left(\frac{N_A + N_D}{N_A N_D}\right)V_{bi}}$$

- $x_n$: depletion depth on n-side, $x_p$: depletion depth on p-side

- Charge neutrality: $N_A x_p = N_D x_n$

Forward and Reverse Bias

**Forward bias**: External voltage $V_F$ counteracts the built-in potential → current increases exponentially:

$$I = I_0\left[\exp\left(\frac{qV}{k_BT}\right) - 1\right]$$

**Reverse bias**: Depletion region widens; only minority carrier current flows → very small current until breakdown.

Breakdown Mechanisms

- **Zener breakdown**: Band-to-band tunneling under strong electric field. Occurs at high doping concentrations

- **Avalanche breakdown**: Carrier multiplication via impact ionization. Occurs at lower doping concentrations

6. Bipolar Junction Transistor (BJT)

NPN BJT Structure and Operation

An NPN BJT consists of three semiconductor regions: n-type, p-type, n-type:

- **Emitter**: Heavily doped, injects carriers

- **Base**: Very thin (hundreds of nm to a few μm), p-type

- **Collector**: Wide region, lightly doped

In forward active mode, the emitter-base is forward biased, and the base-collector is reverse biased:

$$I_C = \beta I_B, \quad I_E = I_C + I_B = (\beta + 1)I_B$$

Current gain $\beta$ typically ranges from 50 to 500.

Transit Frequency

$$f_T = \frac{g_m}{2\pi(C_{BE} + C_{BC})}$$

High-speed BJTs achieve $f_T > 100$ GHz (HBT, SiGe BiCMOS).

7. MOS Capacitor and MOSFET

MOS Structure

The Metal-Oxide-Semiconductor structure is the foundation of modern VLSI:

- **Gate (Metal/Poly-Si)** / **Gate Oxide (SiO2 or High-k)** / **Semiconductor (Si)**

Three Operating Modes

For NMOS with p-type Si substrate:

1. **Accumulation**: $V_G < 0$, holes accumulate at the surface

2. **Depletion**: $0 < V_G < V_{th}$, depletion region forms at the surface

3. **Inversion**: $V_G > V_{th}$, electron channel forms at the surface

Threshold Voltage

$$V_{th} = V_{FB} + 2\phi_F + \frac{Q_{dep}}{C_{ox}}$$

- $V_{FB}$: Flatband voltage

- $\phi_F = (k_BT/q)\ln(N_A/n_i)$: Fermi potential

- $Q_{dep}$: Depletion charge

- $C_{ox} = \varepsilon_{ox}/t_{ox}$: Oxide capacitance per unit area

MOSFET Drain Current Model

**Linear region** ($V_{DS} < V_{GS} - V_{th}$):

$$I_D = \mu_n C_{ox}\frac{W}{L}\left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right]$$

**Saturation region** ($V_{DS} \geq V_{GS} - V_{th}$):

$$I_D = \frac{\mu_n C_{ox}}{2}\frac{W}{L}(V_{GS} - V_{th})^2(1 + \lambda V_{DS})$$

$\lambda$ is the channel length modulation coefficient, and $W/L$ is the channel width-to-length ratio.

8. CMOS Technology

CMOS Inverter

A CMOS inverter connects PMOS and NMOS in series as a basic logic gate:

- Input LOW: PMOS ON, NMOS OFF → Output HIGH

- Input HIGH: PMOS OFF, NMOS ON → Output LOW

- **Ideally zero static power dissipation**

CMOS Power Dissipation

$$P_{total} = P_{dynamic} + P_{static}$$

**Dynamic power**: $P_{dyn} = \alpha C_{load} V_{DD}^2 f$

- $\alpha$: activity factor, $C_{load}$: load capacitance, $f$: clock frequency

**Static power (leakage)**: Subthreshold current, BTBT (band-to-band tunneling), etc.

Dennard Scaling

When channel length is scaled by $1/\kappa$:

- Area decreases by $1/\kappa^2$

- Speed improves by factor $\kappa$

- **Power density**: Theoretically constant

However, below 10 nm, Dennard scaling has broken down and power density has surged, causing the "dark silicon" problem.

FinFET (3D Transistor)

Introduced at the 22 nm node, FinFET forms the channel as a 3D fin structure:

- Gate wraps around 3 sides of the channel → greatly reduced leakage current

- Suppresses short-channel effects (SCE)

- Higher drive current for the same footprint area

GAA (Gate-All-Around) FET

The next-generation structure, introduced/being introduced in Samsung 3 nm and TSMC 2 nm processes:

- Gate completely surrounds the channel 360 degrees (nanosheet/nanowire)

- Better electrostatic control than FinFET

- CFET (Complementary FET): NMOS/PMOS stacked vertically

9. Semiconductor Fabrication

Process Flow Overview

Raw Si → Polysilicon → CZ Growth → Wafer → Epitaxy

→ Lithography → Etch → Ion Implantation → Anneal → Deposition (CVD/PVD)

→ CMP → Metal Interconnect → Packaging → Test

Lithography

Modern lithography advances by shortening the light source wavelength:

- **DUV (Deep Ultraviolet)**: 193 nm ArF laser (current mainstream, with multi-patterning)

- **EUV (Extreme Ultraviolet)**: 13.5 nm source, ASML NXE/EXE systems

- EUV single patterning enables sub-3 nm features

Resolution: $R = k_1\lambda/NA$ (Rayleigh criterion)

Ion Implantation

Dopant atoms are accelerated as an ion beam and implanted into silicon:

- Energy: tens to thousands of keV

- Dose: $10^{11}$~$10^{16}$ cm$^{-2}$

- Post-implant annealing (thermal processing) repairs crystal damage

Key Deposition Processes

- **Thermal Oxidation**: Grows SiO2 gate oxide

- **CVD (Chemical Vapor Deposition)**: Polycrystalline Si, nitride films, Low-k dielectrics

- **ALD (Atomic Layer Deposition)**: High-k dielectrics (HfO2), uniform ultra-thin films

- **PVD/Sputtering**: Metal interconnects (W, Cu, Ru)

CMP (Chemical Mechanical Polishing)

CMP planarizes multi-layer structures using a slurry (abrasive liquid) and polishing pad, achieving flatness at the nanometer level. CMP step count increases with the complexity of 3D structures.

Leading-Edge Process Nodes (2026)

| Company | Current Node | Next Generation |

| ------- | --------------------- | --------------- |

| TSMC | 3 nm (N3E), 2 nm (N2) | 1.4 nm (A14) |

| Samsung | 3 nm GAA, 2 nm | 1.4 nm |

| Intel | Intel 3 (~3 nm) | Intel 18A |

10. Optoelectronic Devices

LED (Light Emitting Diode)

In direct bandgap semiconductors (GaAs, GaN, InGaAs) under forward bias:

1. Electrons recombine from the conduction band to the valence band

2. A photon is emitted with energy equal to $E_g$

Emission wavelength: $\lambda = hc/E_g$ (nm)

High-efficiency blue LEDs are implemented with InGaN/GaN structures (Shuji Nakamura, Nobel Prize 2014).

Solar Cell

Operation of a p-n junction solar cell:

1. Photon absorption → electron-hole pair generation

2. Built-in potential drives electrons to the n-side and holes to the p-side

3. Current is supplied to the external circuit

Single-junction Si solar cell theoretical efficiency limit (Shockley-Queisser): ~29%

Multi-junction III-V solar cells: over 47% achieved (concentrator type)

CCD and CMOS Image Sensors

- **CCD**: Transfers charge in a bucket-brigade fashion. High image quality, high power consumption

- **CMOS sensor**: Each pixel contains active circuitry. Low power, fast readout, dominant in smartphones

11. Latest Semiconductor Trends

Limits of Moore's Law

Moore's Law (doubling of transistor count every two years) is approaching physical limits:

- Quantum tunneling intensifies at gate lengths of a few nm

- Heat dissipation limits (power density in the hundreds of W/cm²)

- Exponentially increasing process costs

3D Integration

**HBM (High Bandwidth Memory)**: DRAM dies stacked vertically, connected by TSV (Through-Silicon Via) → bandwidth of several TB/s.

**Chiplet**: Separate dies manufactured by function and integrated in a single package (adopted by AMD, Intel, Apple).

GaN Power Devices

Gallium nitride's wide bandgap ($E_g = 3.4$ eV) and high electron mobility:

- Optimal for high-voltage, high-frequency power conversion

- GaN-on-SiC, GaN-on-Si substrates

- Spreading to 65 W+ USB-PD chargers and server PSUs

AI-Dedicated Semiconductors

- **NPU (Neural Processing Unit)**: Accelerates matrix operations, low-power inference

- **TPU (Tensor Processing Unit)**: Designed by Google, systolic array architecture

- **HBM + Compute Die**: Core architecture of AI accelerators (NVIDIA H100, AMD MI300)

12. Key Formula Summary

| Item | Formula |

| ------------------------------- | ---------------------------------------------- |

| Intrinsic carrier concentration | $n_i = \sqrt{N_c N_v}\exp(-E_g/2k_BT)$ |

| Mass action law | $np = n_i^2$ |

| Built-in potential | $V_{bi} = (k_BT/q)\ln(N_A N_D / n_i^2)$ |

| Diode current | $I = I_0[\exp(qV/k_BT)-1]$ |

| MOSFET saturation current | $I_D = (\mu_n C_{ox}/2)(W/L)(V_{GS}-V_{th})^2$ |

| Dynamic power | $P_{dyn} = \alpha C V_{DD}^2 f$ |

Quiz

**Answer**: Because silicon is an indirect bandgap semiconductor.

**Explanation**: In an indirect bandgap material, electron-hole recombination requires a phonon to conserve momentum, making photon emission very unlikely. Most energy is dissipated as heat instead. By contrast, direct bandgap semiconductors like GaAs and GaN undergo recombination without a change in momentum, efficiently emitting photons. This is why virtually all practical LEDs use III-V compound semiconductors rather than silicon.

**Answer**: Several short-channel effects emerge.

**Explanation**: The most important are Drain-Induced Barrier Lowering (DIBL), threshold voltage roll-off (Vth decreases as channel shortens), subthreshold slope degradation (the SS increases beyond the 60 mV/decade ideal limit), and increased gate oxide tunneling current. These effects degrade transistor performance and increase leakage. They are the primary motivation for transitioning from planar MOSFETs to FinFET and then to GAA structures as technology nodes shrink.

**Answer**: It forms from the balance between diffusion driven by carrier concentration gradients and the drift caused by the resulting internal electric field.

**Explanation**: When p-type and n-type semiconductors are brought into contact, electrons diffuse from n to p and holes diffuse from p to n due to concentration gradients. The ionized donor (+) and acceptor (-) ions left behind form a space charge region. The electric field generated by this space charge opposes further diffusion. At thermal equilibrium, when the diffusion current and drift current exactly balance, the resulting potential difference is the built-in potential.

**Answer**: Because PMOS and NMOS operate complementarily, there is no direct current path from VDD to GND in steady state.

**Explanation**: In a CMOS inverter, when the input is HIGH, only the NMOS is ON and the PMOS is OFF. When the input is LOW, only the PMOS is ON and the NMOS is OFF. Therefore, in the ideal case, there is no direct current path between the supply (VDD) and ground (GND), and static power dissipation is essentially zero. In real devices, subthreshold leakage current and gate tunneling current exist, but these do not significantly compromise the low-power advantage of CMOS at larger nodes.

**Answer**: Because the gate controls the channel from multiple sides, greatly improving electrostatic control.

**Explanation**: In a planar MOSFET, the gate applies an electric field to only one side (top) of the channel. In a FinFET, the gate wraps around 3 sides of the fin-shaped channel. This superior "electrostatic control" means the drain's electric field is effectively shielded by the gate field, greatly reducing DIBL and Vth roll-off. GAA (Gate-All-Around) takes this further by surrounding the channel 360 degrees, enabling continued scaling below the FinFET limit.

References

- **Sze, S.M. & Ng, K.K.** — _Physics of Semiconductor Devices_ (3rd Ed.), Wiley

- **Neamen, D.A.** — _Semiconductor Physics and Devices: Basic Principles_ (4th Ed.), McGraw-Hill

- **Streetman, B.G. & Banerjee, S.** — _Solid State Electronic Devices_, Pearson

- **MIT OCW 6.012** — Microelectronic Devices and Circuits (Prof. Jesús del Alamo)

- **TSMC Technology Overview** — tsmc.com/technology

- **ITRS/IRDS Roadmap** — irds.ieee.org

_If you found this post helpful, check out the next in the series: "Analog Circuit Design Complete Guide."_