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Prologue - The "FPGAs Are Expensive and Hard" Cliche Broke in 2026

Until the mid-2010s, "FPGA" was a synonym for "expensive chips, more expensive tools, and locked licenses". You had to install a 30+ GB free edition of Xilinx Vivado, the same for Altera Quartus. Synthesis was a black box. No cloud builds. Change one line and wait 30 minutes - that was daily life.

The 2026 picture is different. iCE40, ECP5 and parts of Gowin can go from RTL to bitstream with a fully open chain: **Yosys + NextPnR + IceStorm / Project Trellis / Apicula**. Open RISC-V cores - **PULPino, Rocket, BOOM, VexRiscv, Ariane (CVA6), OpenTitan** - are all in the open. SBCs start at $30: **VisionFive 2, Milk-V Mars, BeagleV-Fire, HiFive Premier P550, Banana Pi BPI-F3, LicheePi 4A**.

ASIC is within reach too. **Tiny Tapeout** mounts hobbyist and student designs on SkyWater 130nm or GlobalFoundries 180nm shuttles for $50 to $300. **OpenROAD** runs RTL all the way down to GDSII with open EDA only.

This post lays out the whole terrain - FPGA vendors, open toolchains, boards, RISC-V cores, HDL languages, simulators, formal verification, open ASIC, and the Korean/Japanese flow - as of 2026.

1. FPGA Fundamentals - LUT, FF, BRAM, DSP, Clock Domains

An FPGA (Field-Programmable Gate Array) is a **reconfigurable array of digital logic**. Five core resources matter.

| Resource | Role | Unit |

| --- | --- | --- |

| LUT (Look-Up Table) | 4 to 6 input truth table, implements any combinational function | iCE40 4-LUT, ECP5 4-LUT, 7-series 6-LUT |

| FF (Flip-Flop) | Synchronous register, typically one per LUT | LUT-FF pair |

| BRAM (Block RAM) | 18 to 36 kbit dual-port memory blocks | iCE40 4 kbit EBR, ECP5 18 kbit EBR |

| DSP slice | Multiply/accumulate units, for DSP and AI acceleration | iCE40 almost none, ECP5 18 by 18, 7-series DSP48 |

| Clock / PLL | Clock distribution, frequency synthesis | Usually 4 to 8 global clocks |

LUT count is the first-order proxy for chip size, but **BRAM and DSP determine applications**. Video and AI accelerators stall on DSPs; cache- or FIFO-heavy designs hit BRAM first.

iCE40 HX8K: 7,680 LUT4, 7,680 FF, 32 x 4 kbit BRAM = 128 kbit, no DSP

iCE40 UP5K: 5,280 LUT4, 5,280 FF, 30 x 4 kbit + 4 x 128 kbit SPRAM = ~640 kbit, 8 DSP

ECP5 LFE5UM-85F: 84K LUT4, 84K FF, 208 x 18 kbit = ~3.7 Mbit, 156 DSP

Artix-7 XC7A100T: 101K LUT6, 126K FF, 4.86 Mbit BRAM, 240 DSP48

"Which size chip should I buy?" is a question that only synthesis can answer. The rough rule: **hobby learning sits at 5K to 10K LUT (iCE40 HX/UP5K, Tang Nano 9K), academic and RISC-V soft cores at 25K to 85K LUT (ECP5, Cyclone 10), and serious SoCs at 100K+ (Artix-7, Zynq)**.

2. FPGA Vendor Landscape - AMD/Xilinx, Intel/Altera, Lattice, Microchip, GOWIN, EFINIX

In 2025 Intel **spun off Altera and put it back up as an independent company**, while AMD's 2022 Xilinx acquisition was fully absorbed into **AMD Adaptive Computing**. The six 2026 vendors are these.

| --- | --- | --- | --- | --- |

Key 2026 trends.

- **AMD Versal ACAP** - FPGA + ARM + AI Engine on one chip. 4nm process, HBM integration. AI inference for the datacenter.

- **Lattice Avant** - Lattice's first mid-range FPGA, announced 2023, in production 2025. About 5x the logic of ECP5.

- **Microchip PolarFire SoC** - 5-core RISC-V (four U54 + one E51) plus FPGA. Used in BeagleV-Fire.

- **GOWIN GW5A** - Arora V at 5nm, very active in the Korean and Japanese maker scene.

For open toolchains, **Lattice is effectively the standard**. iCE40 (IceStorm), ECP5 (Project Trellis), MachXO (Project Oxide): the full lineup flows through Yosys/NextPnR, and Lattice ships Yosys as an option inside Radiant. GOWIN entered via **Apicula** plus nextpnr-himbaechel for parts of the LittleBee/Arora V family.

3. Yosys - The De Facto Open Synthesizer

**Yosys**, written by Claire Wolf (formerly Clifford Wolf) since 2012, is a Verilog synthesizer under the ISC license. Version 0.45 is the 2026 stable.

Yosys is not just a synthesizer - it is a **modular RTL to gate-level pipeline**. You start with read_verilog and run passes like proc, opt, techmap and abc, finishing with write_verilog or write_blif.

One-liner synthesis targeting iCE40

yosys -p "synth_ice40 -top top -json out.json" design.v

A more detailed flow

yosys -p "

read_verilog design.v

hierarchy -check -top top

proc; opt; fsm; opt

memory_bram -rules ice40.txt

techmap; opt

abc -lut 4

clean

write_json out.json

Key features.

- **Multiple backends** - iCE40, ECP5, Xilinx 7-series (experimental), Gowin, Intel (experimental), Nexus, ASIC (ABC + Liberty)

- **SystemVerilog coverage** - Verilog 2005 is complete; SV 2017 is partial (parameters, partial interface). Full SV via **slang + Yosys** or the **sv2v** translator.

- **Verific frontend** - commercial parser. Yosys + Verific gives full SV/VHDL coverage. Not open.

- **Yosys cell library** - includes simulation models.

In 2024 **YosysHQ** took over the Yosys mainline and built the **Tabby CAD Suite** (Yosys + Verific + SymbiYosys with commercial support) as a business model. The core stays **ISC open source**.

4. NextPnR - Modern Place and Route, Replaces arachne-pnr

**NextPnR** (2018+) is the place-and-route counterpart to Yosys. It replaced the older **arachne-pnr** (iCE40 only, simple simulated annealing).

What NextPnR brought.

- **Timing-aware P&R** - static timing analysis feeds directly into the placement and routing loop.

- **Multiple devices** - iCE40, ECP5, Nexus (MachXO5), Gowin (via himbaechel), experimental Xilinx.

- **HeAP placer + router** - holds up under bigger designs.

- **GUI** - visualizes placement.

The flow is simple.

Yosys synthesis

yosys -p "synth_ice40 -top top -json top.json" top.v

NextPnR place and route

nextpnr-ice40 --hx8k --package ct256 \

--json top.json \

--pcf top.pcf \

--asc top.asc

icepack: ASCII to bitstream

icepack top.asc top.bin

iceprog: program the board

iceprog top.bin

The ECP5 flow has the same shape.

yosys -p "synth_ecp5 -top top -json top.json" top.v

nextpnr-ecp5 --25k --package CABGA381 \

--json top.json --lpf top.lpf \

--textcfg top.config

ecppack --svf top.svf top.config top.bit

ujprog top.bit # or openFPGALoader

Gowin is nearly identical.

yosys -p "synth_gowin -top top -json top.json" top.v

nextpnr-himbaechel --device GW1NR-LV9QN88PC6/I5 \

--json top.json --vopt cst=top.cst \

--write top_pnr.json

gowin_pack -d GW1N-9C -o top.fs top_pnr.json

openFPGALoader -b tangnano9k top.fs

**NextPnR 0.7+** (2025) added a multi-threaded router that cuts P&R time on 100K LUT designs by more than half.

5. Project IceStorm, Project Trellis, Project NX/Apicula - Bitstream Reverse Engineering

The real difficulty in an open toolchain is the **bitstream format**. Synthesis and P&R are algorithmic problems, but the bitstream is bit-level encoding that vendors keep closed. The "projects" exist to crack that.

| --- | --- | --- | --- |

The key two are **IceStorm** and **Project Trellis**. Claire Wolf's **Project IceStorm** (2015) was the seed of everything. She walked the iCE40 bitstream bit by bit and cracked it, and on top of that came the Yosys synth_ice40 backend and arachne-pnr/nextpnr-ice40. David Shah's **Project Trellis** (2017) did the same for ECP5. Without those two, NextPnR would have no targets.

Trends in 2025 to 2026.

- **Project Oxide -> nextpnr-nexus** - partial support for MachXO5/CrossLink-NX. Lattice itself collaborates on parts.

- **Apicula** - Robert Ou and others cracked the GOWIN GW1N family; GW2A is in progress. Tang Nano 9K/20K is production-usable.

- **prjpolarfire** - PolarFire bitstream analysis is starting. It will take time.

The takeaway: **even without vendor cooperation you can crack the bitstream**, but you need human-hours to do it.

6. Open FPGA Boards - iCEbreaker, OrangeCrab, Tang Nano, ECPIX-5, Arty A7

A catalogue of boards that flow through the open toolchain in 2026.

**iCE40 family (easiest entry)**

| --- | --- | --- | --- | --- |

**ECP5 family (RISC-V soft core practical zone)**

| --- | --- | --- | --- |

**Gowin family (cheapest)**

| --- | --- | --- | --- |

| Tang Primer 20K | GW2A-18 | $50 | Bigger LUT count, Pmod |

**Xilinx (partial open chain, Vivado primary)**

| --- | --- | --- | --- |

**Intel/Altera**

| --- | --- | --- | --- |

| CYC1000 | Cyclone 10 LP | $50 | Trenz, compact |

A reasonable ladder: stage one is **iCEbreaker (iCE40-UP5K, $50)**, stage two is **ULX3S or OrangeCrab (ECP5, $115 to $150)**, and stage three is **Arty A7-100T or Zybo Z7-20**. Tang Nano 9K is the best "I want to start with $20" option.

7. RISC-V - From the ISA to Extension Sets

**RISC-V** is an open ISA started at UC Berkeley in 2010. The RISC-V Foundation (now RISC-V International) launched in 2015, and by 2026 the standards have settled.

| Extension | Meaning | Notes |

| --- | --- | --- |

| RV32I / RV64I | 32/64-bit base integer | Required |

| M | Multiply and divide | Effectively required |

| A | Atomic | Required for SMP and multicore |

| F / D / Q | Float 32/64/128 | Partial adoption |

| C | Compressed (16-bit insns) | About 1.5x code size win |

| B | Bit manipulation (Zba/Zbb/Zbs) | Ratified 2021 |

| V | Vector | Ratified 2021, core to AI |

| Zicsr / Zifencei | CSR / fence.i | Required by systems |

| H | Hypervisor | Ratified 2023 |

| Zk* | Scalar crypto | Ratified 2021 |

The typical "RV64GC" profile equals RV64IMAFDCZicsr_Zifencei. It is the Linux distro standard.

**RVA23**, ratified in 2025, is the 2026 datacenter and mobile baseline. RVA23 mandates V (Vector 1.0), B, Zk*, H and Zicboz. Android RISC-V ports target RVA23.

8. Open RISC-V Cores - PULPino, Rocket, BOOM, Ariane, VexRiscv, OpenTitan

By 2026 open-source RISC-V CPU core IP is essentially a "pick one" menu.

| --- | --- | --- | --- | --- |

How to choose.

- **"Try RISC-V on an iCE40-UP5K"** -> PicoRV32 or SERV.

- **"Boot Linux on ECP5"** -> VexRiscv with LiteX, or Rocket Chip.

- **"Industrial RV32 MCU IP"** -> CV32E40P (PULPino) or Ibex.

- **"Academic OoO core"** -> BOOM or NaxRiscv.

- **"Secure root of trust"** -> OpenTitan.

**LiteX** (Florent Kermarrec) is a framework that builds VexRiscv-centered SoCs in five minutes. It is the fastest way to boot Linux on ECP5/ULX3S/OrangeCrab/Tang Nano.

9. SiFive, Andes, Codasip - Commercial RISC-V IP

**SiFive** (founded by Berkeley alumni in 2015) is the flagship commercial RISC-V IP vendor. The 2026 lineup looks like this.

| --- | --- | --- | --- |

| Automotive | S26, S2C26 | ASIL-B/D | ISO 26262 |

The 2025 **SiFive P870-D** is a datacenter-class 16-core RV64GCV at 5GHz. In the Intel Lunar Lake era, RISC-V is taking aim at laptops and servers.

Other commercial IP.

- **Andes Technology** - Taiwan, AndeStar V5 ISA (RISC-V compatible with extensions). Cores: Andriy N25/A25/AX65/AX27.

- **Codasip** - Czech Republic, custom RISC-V core generator + Codasip Studio.

- **Cortus** - France, APS25.

- **Esperanto Technologies** - ET-SoC-1, a 1088-core RISC-V AI inference chip.

- **Tenstorrent** - Jim Keller's company. Ascalon (16-wide OoO RV64), pushing into laptop SoCs.

The 2026 headline is **"RV64 server-class core"**. For the first time, RISC-V cores aimed seriously at ARM Neoverse exist.

10. RISC-V SBCs - VisionFive 2, Milk-V, BeagleV, HiFive, Banana Pi, LicheePi

Physical RISC-V computers (boards) exist at essentially every price point in 2026.

| --- | --- | --- | --- | --- |

| **Milk-V Mars CM** | JH7110 | 4 x U74 | $40 | CM4 form factor |

| **Milk-V Pioneer** | SG2042 | 64 x C920 | $1500 | Mainboard form, desktop |

| **Pine64 Star64** | JH7110 | 4 x U74 | $70+ | Pine64 ecosystem |

| **BeagleV-Ahead** | TH1520 | 4 x C910 | $150 | BeagleBoard.org |

| **SiFive HiFive Unmatched** | FU740 | 4 x U74 + 1 x S7 | (EOL) | 2021 |

| **Sipeed LicheePi 3A** | TH1520 | 4 x C910 | $80 | Lightweight |

Picked by performance and software maturity.

- **Desktop replacement attempt** - Milk-V Pioneer, HiFive Premier P550.

- **Hobby and home server** - VisionFive 2, Milk-V Mars, Pine64 Star64. Ubuntu/Debian/Fedora packages are plentiful.

- **Digital design learning with FPGA** - BeagleV-Fire.

- **Vector accelerator beta** - Banana Pi BPI-F3, LicheePi 4A.

The real friction for RISC-V SBCs in 2026 is still **GPU drivers** and **kernel V-extension support**. The mainline kernel landed RVV 1.0 but user-space libraries are still catching up.

11. BeagleV-Fire and PolarFire SoC - FPGA + RISC-V in One Package

**BeagleV-Fire** (2024) is a BeagleBoard.org board built around the **Microchip PolarFire SoC MPFS025T-FCSG325E**. The package contains:

- 4 x SiFive U54 RV64GC Linux-capable cores at 600MHz

- 1 x SiFive E51 RV64IMAC monitor core

- ~25K LUT + 68 LSRAM (PolarFire FPGA fabric)

- Integrated memory controller, PCIe, USB

The point of this board is that it is **the RISC-V equivalent of Zynq**. Like Zynq fuses ARM Cortex-A with FPGA, this one fuses RISC-V with FPGA, so software runs Linux while acceleration runs on the FPGA. PolarFire is also **flash-based**, so it boots immediately (SRAM-based Xilinx parts need bitstream loading time).

After booting RISC-V Linux on BeagleV-Fire, swap the FPGA bitstream

sudo mtd-utils flashcp custom.spi /dev/mtd-fpga

or use the BeagleV-Fire gateware update tool

sudo /opt/microchip/fpga-config-tool/fct \

--bitstream custom.dat --slot golden

sudo reboot

Microchip pushes **Libero SoC** (closed) as the primary flow, but the BeagleV-Fire community is opening a path to run **VexRiscv + LiteX** on PolarFire.

12. HDL Languages - Verilog, SystemVerilog, VHDL, Chisel, SpinalHDL, Amaranth, Veryl

The HDL landscape in 2026 splits into five threads.

**1. Classical Verilog / SystemVerilog (industry standard)**

// SystemVerilog 2017 - simple register

module reg8 (

input logic clk,

input logic rst_n,

input logic [7:0] din,

output logic [7:0] dout

);

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) dout <= 8'h00;

else dout <= din;

end

endmodule

SV 2017 added the industry essentials: `logic`, `always_ff/comb`, `interface`, `package`, `bind`, and assertions (SVA). The 2023 standard is effectively a minor update.

**2. VHDL 2019**

entity reg8 is

port (

clk : in std_logic;

rst_n : in std_logic;

din : in std_logic_vector(7 downto 0);

dout : out std_logic_vector(7 downto 0)

);

end entity;

architecture rtl of reg8 is

begin

process (clk, rst_n) is

begin

if rst_n = '0' then

dout <= (others => '0');

elsif rising_edge(clk) then

dout <= din;

end if;

end process;

end architecture;

Strong in Europe, defense and aerospace. **GHDL** is the open simulator and `ghdl-yosys-plugin` solves synthesis.

**3. Chisel (Scala based, UC Berkeley)**

class Reg8 extends Module {

val io = IO(new Bundle {

val din = Input(UInt(8.W))

val dout = Output(UInt(8.W))

})

val r = RegInit(0.U(8.W))

r := io.din

io.dout := r

}

Chisel is a **Scala embedded DSL**. Rocket Chip, BOOM and the entire Chipyard ecosystem live on Chisel. The output goes through FIRRTL to SystemVerilog. Chisel 6 (2024) is built on Scala 2.13/3.

**4. SpinalHDL (Scala based, VexRiscv ecosystem)**

class Reg8 extends Component {

val io = new Bundle {

val din = in UInt(8 bits)

val dout = out UInt(8 bits)

}

val r = Reg(UInt(8 bits)) init(0)

r := io.din

io.dout := r

}

Same philosophy as Chisel but lighter syntax and faster simulation. VexRiscv and NaxRiscv were built on top.

**5. Python HDLs - Amaranth (formerly nMigen), Migen, MyHDL, PyMTL**

Amaranth

from amaranth import *

class Reg8(Elaboratable):

def __init__(self):

self.din = Signal(8)

self.dout = Signal(8)

def elaborate(self, platform):

m = Module()

m.d.sync += self.dout.eq(self.din)

return m

Amaranth (M-Labs, formerly nMigen) integrates directly with Yosys. Parts of LiteX use Amaranth as well.

**6. Veryl (Rust-style, 2023+)**

module reg8 (

clk: input clock,

rst_n: input reset,

din: input logic<8>,

dout: output logic<8>,

) {

always_ff (clk, rst_n) {

if_reset {

dout = 0;

} else {

dout = din;

}

Veryl transpiles to Verilog. Modern language features: module imports, type inference, namespaces.

**7. CIRCT (MLIR based, in LLVM)**

CIRCT is a **circuit IR** inside LLVM. It hosts several dialects: FIRRTL, HW, SV, Calyx. By 2026 Chisel has moved almost entirely to the CIRCT backend.

A reasonable ladder: stage one is SystemVerilog (industry standard), stage two is Chisel or SpinalHDL (RISC-V SoC ecosystem), stage three is Amaranth or Veryl.

13. Verilator, Icarus, GHDL, Cocotb - Simulators

Before burning RTL onto a chip, you **simulate** it. The 2026 toolset.

| --- | --- | --- | --- | --- |

Verilator flow.

Synthesizable Verilog to C++ compile

verilator --cc design.v --exe sim_main.cpp \

--trace --build -j 0

Run the simulation

./obj_dir/Vdesign

Inspect waveforms in GTKWave or Surfer

gtkwave dump.vcd

**Cocotb** (since 2013) is a Python coroutine testbench framework. The 2026 stable is 1.9.

tb_reg8.py

from cocotb.clock import Clock

from cocotb.triggers import RisingEdge

@cocotb.test()

async def test_reg8(dut):

cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())

dut.rst_n.value = 0

await RisingEdge(dut.clk)

dut.rst_n.value = 1

dut.din.value = 0xA5

await RisingEdge(dut.clk)

assert dut.dout.value == 0xA5

A minimal Makefile

SIM = verilator

TOPLEVEL_LANG = verilog

VERILOG_SOURCES = $(PWD)/reg8.sv

TOPLEVEL = reg8

MODULE = tb_reg8

include $(shell cocotb-config --makefiles)/Makefile.sim

For **waveform viewers**, **GTKWave** has been the standard, but in 2024 to 2025 **Surfer** (a new Rust wave viewer) is gaining ground fast. It has a WASM build so it runs in the browser.

14. SymbiYosys and Formal Verification - Beyond Simulation

Simulation needs you to write the input cases. **Formal verification** **mathematically proves a property holds for all cases**.

**SymbiYosys** (YosysHQ) is the formal verification driver on top of Yosys. Internally it dispatches to SMT solvers like Z3, Yices2, Boolector and CVC4.

// add4.sv with an SVA property

module add4 (

input logic [3:0] a, b,

output logic [4:0] s

);

assign s = a + b;

// Property: s is never larger than 30 (signed interpretation)

property no_overflow_msb;

@(posedge $time) (s <= 30);

endproperty

assert property (no_overflow_msb);

endmodule

add4.sby

[tasks]

prove

[options]

prove: mode prove

prove: depth 20

[engines]

prove: smtbmc z3

[script]

read -formal add4.sv

prep -top add4

[files]

add4.sv

sby -f add4.sby prove

Result: PASS - or a counterexample VCD

Formal verification is strongest on **bus protocols like AXI and Wishbone** and on **crypto modules**. Symbiotic EDA's **Wishbone formal property** and **AXI VIP** are the references.

YosysHQ bundles **Tabby CAD Suite** (Verific full SV/VHDL parser + Yosys + SBY + commercial support). The open SBY remains free.

15. Standard Buses - AXI, AXI-Lite, Wishbone, TileLink

Inside an SoC, IP blocks talk over **standard buses**.

| --- | --- | --- | --- |

Open RISC-V SoCs typically use **TileLink** (Rocket Chip, Chipyard) or **Wishbone** (LiteX, VexRiscv) and convert to AXI only at external interfaces. Open AXI to Wishbone and AXI to TileLink bridges exist.

**IP-XACT** (IEEE 1685) is the IP metadata standard. It describes ports, registers and memory maps in XML so RTL wrappers can be generated automatically. Kactus2 is a representative open tool.

16. Open ASIC - OpenROAD, SkyWater 130nm, GlobalFoundries 180nm, Tiny Tapeout

FPGAs are reconfigurable, but **ASICs** (application-specific integrated circuits) are permanent once taped out. The open ASIC flow became viable starting in 2020.

**OpenROAD** (DARPA IDEA, UCSD/UMich) is an open EDA flow from RTL all the way to GDSII. Yosys handles synthesis, OpenROAD handles floorplan, place, CTS, route and DRC/LVS.

OpenROAD flow scripts

git clone https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts

cd OpenROAD-flow-scripts

./build_openroad.sh

Add a design

cp -r designs/gcd flow/designs/sky130hd/my_design

Edit the Makefile config

make DESIGN_CONFIG=./designs/sky130hd/my_design/config.mk

**PDKs** (process design kits) provide device models and rules to fabricate a chip. Two open PDKs matter most.

| --- | --- | --- | --- |

**Tiny Tapeout** (Matt Venn, 2022+) is the decisive change. Sky130 collects user designs as **tiles** onto one chip and ships each contributor a PCB. The 2026 shuttle prices: 1x1 tile = $50, 2x2 = $200, 8x2 = $300.

A Tiny Tapeout design compresses to a single Verilog module

module tt_um_my_design (

input wire [7:0] ui_in, // 8 inputs (switches/buttons)

output wire [7:0] uo_out, // 8 outputs (LEDs)

input wire [7:0] uio_in, // bidirectional in

output wire [7:0] uio_out, // bidirectional out

output wire [7:0] uio_oe, // bidirectional enable

input wire ena, // enable

input wire clk, // clock

input wire rst_n // reset

);

// your design here

endmodule

**OpenLane** (Efabless) packages SkyWater + OpenROAD into one flow. **Mflowgen** (UT Austin) plays a similar role. OpenLane 2, rewritten in Python, lands in 2026.

The Efabless **caravel** chip is RISC-V (PicoRV32) plus roughly a 10mm² user slot. The MPW shuttle (multi-project wafer) using caravel runs a few times a year. For the first time students and small teams can own "my ASIC".

17. OpenTitan, Caliptra - Open Hardware for Security Roots of Trust

**OpenTitan** (lowRISC + Google, 2019+) is an open **security root of trust** chip design. It puts an Ibex RV32IMC core, AES/SHA/HMAC/PRNG accelerators, a life cycle manager, OTP fuses, USB and SPI onto one chip. It is the open answer to Google Titan (Chromebook security chip) and Apple T2.

In 2024 Google announced a production OpenTitan-based chip. By 2026, datacenter NICs, server BMCs and IoT gateways are adopting OpenTitan as a root of trust.

**Caliptra** (OCP, Microsoft/Google/AMD/NVIDIA, 2022+) is a root-of-trust IP block that ships inside datacenter accelerators and SoCs. It reuses parts of OpenTitan. Open Compute Project standard.

The point: **"security chips can be open too"**. Moving from closed security (TPM makers built chips no one could inspect) to open verifiable security.

18. Chipyard, LiteX, Caravel - RISC-V SoC Integration Frameworks

Writing "core + memory + UART + SPI + Ethernet" from scratch every time is wasteful. SoC integration frameworks fill that gap.

**Chipyard** (UC Berkeley, 2018+) is a Chisel-based RISC-V SoC generator. It composes Rocket, BOOM or CVA6 cores with L2 caches, accelerators (NVDLA, Gemmini), memory controllers and peripherals.

// Chipyard config

class MyConfig extends Config(

new boom.common.WithNLargeBooms(1) ++

new freechips.rocketchip.subsystem.WithNBigCores(2) ++

new chipyard.config.AbstractConfig

)

The Chipyard workflow targets simulators (VCS/Verilator), FPGA (FireSim) and ASIC (Hammer) at once. **FireSim** (AWS F1) runs RISC-V SoCs cycle-accurate on cloud FPGAs.

**LiteX** (Florent Kermarrec, 2018+) is a Migen/Amaranth-based SoC generator. VexRiscv or NaxRiscv core, Wishbone bus, LiteDRAM, LiteEth, LiteSDCard and other IP. It is the easiest way to boot Linux on iCEbreaker, ULX3S, OrangeCrab, Arty or Tang Nano.

LiteX + VexRiscv + Linux on ULX3S

git clone https://github.com/litex-hub/linux-on-litex-vexriscv

cd linux-on-litex-vexriscv

./make.py --board=ulx3s --variant=85F --cpu-variant=linux \

--build --load

**Caravel** (Efabless) is the ASIC-shuttle RISC-V wrapper. User area plus a management SoC (PicoRV32 based).

19. Korean FPGA / RISC-V Activity - ETRI, KAIST, Rebellions

Korean FPGA and RISC-V activity is shifting from academic to industrial.

- **ETRI** (Electronics and Telecommunications Research Institute) - RISC-V based system semiconductor research. ETRI demoed a RISC-V Linux board in 2024.

- **KAIST** - digital design courses standardize on SystemVerilog + Vivado. RISC-V courses use Chipyard and Rocket.

- **Seoul National University, POSTECH, Korea University** - RISC-V SoC research.

- **Rebellions** (2020+) - AI inference chips ATOM (gen 1 with GDDR6, gen 2 with HBM). Their control core is RISC-V based. Adopted by SK Telecom's datacenter.

- **FuriosaAI** - Warboy (gen 1, 2021), RNGD (gen 2, 2024). They use their own NPU but evaluate RISC-V as a host.

- **Sapeon** - the SK-affiliated NPU player.

- **DEEPX** - edge AI NPU.

- **Telechips and Silicon Mitus** - exploring RISC-V for automotive and power semiconductors.

The Korean FPGA maker market diversified from Lattice/Xilinx/Intel toward Tang Nano (GOWIN) on price. **Maker Faire Seoul 2025** held workshops for Tang Nano and ULX3S.

Open RISC-V SBCs ship in through Aliexpress and direct buys. VisionFive 2, Milk-V and LicheePi all have active community write-ups on Clien and the RPi Korea forums.

20. Japanese Activity - PEZY-SC, Renesas RZ/Five, AIST OpenTitan

Japan sits in a unique spot for RISC-V and FPGA. ARM Cortex and NEC/Renesas/Toshiba in-house cores were strong, so RISC-V was late, but acceleration since 2024 is real.

- **Renesas RZ/Five (2023)** - the first volume-production RISC-V MPU. Dual Andes AX45MP RV64GC plus RGMII Ethernet. Industrial.

- **Renesas R9A02G021 (2024)** - RISC-V based 32-bit MCU. AndesCore N22.

- **PEZY-SC4 / SC4s** - PEZY Computing's many-core accelerator. The first generation (SC1) was MIPS; later generations use a custom ISA with a RISC-V host candidate. Has placed on the Japan Top500.

- **AIST** (National Institute of Advanced Industrial Science and Technology) - a Japanese OpenTitan port and RISC-V CPU research.

- **Tokyo Tech, Tohoku, Kyoto** - RISC-V SoC, quantum and AI accelerator research.

- **Hayabusa / Konzo Lab (RISC-V board community)** - Tang Nano and iCEbreaker workshops on the Akihabara maker scene.

The interesting note: Japan is strong in **automotive RISC-V**. Renesas has shipped ISO 26262 ASIL-D RISC-V parts. The first industrial case for ARM-to-RISC-V transition in car ECUs is likely to come from Japan.

**METI's** Rapidus 2nm foundry is not RISC-V itself, but Japan reclaiming an advanced node underpins future RISC-V SoC volume.

21. Applications - Retro Computing, HFT, Video, AI, Security

Where open FPGA and RISC-V actually get used.

**1. Retro computing and games (FPGA NES/SNES/MD)**

| Project | Board | Notes |

| --- | --- | --- |

| **MiSTer FPGA** | DE10-Nano (Cyclone V SoC) | NES, SNES, MD, PS1, Amiga, MSX and 200+ systems |

| **Analogue Pocket** | Altera Cyclone 10 | GB/GBC/GBA plus extra cores |

| **MARSx (open)** | ECP5 | In progress |

| **NESCube** | iCE40 | NES on a single chip |

Since 2017 MiSTer has effectively become the retro FPGA standard. Download 200+ open cores onto an SD card and boot.

**2. HFT (high-frequency trading)**

Parsing exchange market data feeds, generating orders, converting FIX to native protocols - all at **nanosecond latency** - relies on Xilinx UltraScale+/Versal. The open chain is almost absent here; Vivado dominates.

**3. Video / image processing**

Live video like HDMI input -> small ML inference -> HDMI output. ECP5 (OrangeCrab) plus a Wuxx HDMI Pmod, or Zybo Z7. Sipeed Tang Mega 138K is attempting 4K60 processing.

**4. AI accelerators**

NVDLA (NVIDIA Deep Learning Accelerator, open), Gemmini (Chipyard) and VTA (TVM) can be synthesized to FPGA. Small models fit on ECP5 85F; large models target Versal AI Edge.

**5. Security root of trust**

OpenTitan ships into datacenter NICs, server BMCs and IoT gateways. ChromeOS Titan-C (OpenTitan based) and Caliptra (OCP) are entering production.

**6. Learning and education**

Writing RV32IMC from scratch has become a standardized course at KAIST/Berkeley/ETH. iCEbreaker + PicoRV32, ULX3S + VexRiscv and Arty + Rocket are the standard combinations.

22. Comparison Matrix - FPGA Boards and RISC-V SBCs in One Table

| --- | --- | --- | --- | --- | --- | --- | --- |

| RISC-V vector | Banana Pi BPI-F3 | SpacemiT K1 | 8 x X60 | 4/8/16GB | $90+ | RVV 1.0 | Software immature |

| RISC-V workstation | Milk-V Pioneer | SG2042 | 64 x C920 | DDR4-3200 | $1500 | 64 cores | Price and power |

23. Learning Roadmap - From Week 0 to a Full Year

A 12-month roadmap for someone entering FPGA and RISC-V for the first time.

**Weeks 1 to 2 - Verilog fundamentals**

- Verilog 2005 syntax, always blocks, registers, FSMs.

- Simulator: iverilog + GTKWave. Or EDA Playground (in-browser).

- Book: Pong P. Chu, "FPGA Prototyping by Verilog Examples".

**Weeks 3 to 6 - First board, first blink, first UART**

- Buy an iCEbreaker or a Tang Nano 9K.

- LED blink -> UART echo -> 7-seg -> VGA.

- Open toolchain (Yosys + NextPnR + IceStorm).

**Weeks 7 to 12 - SystemVerilog + formal verification**

- always_ff/comb, interface, package, SVA.

- Prove simple properties with SymbiYosys.

- Cocotb testbench through Verilator.

**Months 4 to 6 - First RISC-V soft core**

- Burn PicoRV32 onto iCE40-UP5K and run firmware.

- Or burn VexRiscv onto ULX3S and bring up Linux through LiteX.

- Assembly, then GCC, then OpenOCD debugging.

**Months 7 to 9 - Chisel/SpinalHDL or ECP5 SoC**

- Chisel Bootcamp (Berkeley) or a SpinalHDL workshop.

- Simulate Rocket Chip through Chipyard.

**Months 10 to 12 - ASIC flow or RISC-V SBC with accelerator**

- Submit a small design to Tiny Tapeout ($50).

- Or attach an accelerator IP to VisionFive 2 / BeagleV-Fire.

The total bill is $30 (Tang Nano) to $300 (board + ASIC tile) - well within an undergraduate budget. After a year you reach the level of "I wrote a full SoC from RTL".

24. Pitfalls and Common Traps

- **Synthesis vs simulation mismatch** - `initial`, `#delay` and race conditions pass simulation but are ignored or behave differently in synthesis.

- **Clock domain crossing (CDC)** - signals that cross between clocks must be synchronized. Metastability is a real bug. Run a CDC linter and use formal.

- **Timing violations** - the first build may pass while larger designs miss setup/hold. Change NextPnR `--seed`, add pipelining.

- **Out of LUT/FF -> move to ECP5** - the iCE40 5K is not enough for RISC-V Linux; VexRiscv RV32IM typically needs ECP5 25F or larger.

- **Vendor library lock-in** - explicit Vivado primitives (BUFG, IOBUF) do not port to other FPGAs. Prefer inferable code.

- **Trusting simulation alone** - formal, post-synthesis timing reports and on-board measurements all matter.

- **Bitstream encoding differences** - even on the same ECP5 chip, Lattice Diamond and Yosys+nextpnr can produce different bitstreams. Yosys is sometimes conservative on corner cases.

- **RISC-V V extension** - RVV 1.0 is ratified, but GCC/LLVM autovectorization in 2026 is still progressing. You still write intrinsics by hand.

25. Conclusion - Real Democratization of Digital Design

In 2026, digital circuit design is no longer "only for those with expensive EDA licenses".

- A $20 Tang Nano for first blink.

- Free Yosys/NextPnR for any iCE40/ECP5/Gowin bitstream.

- Free Verilator/Cocotb for industrial-grade simulation.

- Free SymbiYosys for formal verification.

- A $50 Tiny Tapeout slot for an ASIC.

- $50 to $1500 of RISC-V SBC choices from desktop to workstation.

On top of that, **open cores** (PicoRV32, VexRiscv, Rocket, BOOM, CVA6, Ibex), **open SoC frameworks** (Chipyard, LiteX), **open PDKs** (SKY130, GF180MCU), and **open RoT** (OpenTitan, Caliptra) drop into your environment with one command line. A single student can touch all of it.

Two gaps remain. First, the open chain for high-density FPGAs (Versal, Stratix 10) is still distant. Second, open PDKs at 7nm and below stay behind NDAs. But for learning, hobbies and small-volume production, open is already enough.

The real message is simple: **"getting your own circuit onto a chip" now costs less than 100 books**. The next step is not more learning. It is making something.

References

- Yosys: https://github.com/YosysHQ/yosys

- NextPnR: https://github.com/YosysHQ/nextpnr

- Project IceStorm: https://github.com/YosysHQ/icestorm

- Project Trellis: https://github.com/YosysHQ/prjtrellis

- Project Oxide (Nexus): https://github.com/gatecat/prjoxide

- Project Apicula (Gowin): https://github.com/YosysHQ/apicula

- SymbiYosys: https://github.com/YosysHQ/sby

- Verilator: https://www.veripool.org/verilator/

- Icarus Verilog: http://iverilog.icarus.com/

- Cocotb: https://www.cocotb.org/

- GTKWave: https://gtkwave.sourceforge.net/

- Surfer waveform viewer: https://surfer-project.org/

- RISC-V International: https://riscv.org/

- Rocket Chip: https://github.com/chipsalliance/rocket-chip

- BOOM: https://github.com/riscv-boom/riscv-boom

- CVA6 (Ariane): https://github.com/openhwgroup/cva6

- CV32E40P: https://github.com/openhwgroup/cv32e40p

- Ibex: https://github.com/lowRISC/ibex

- VexRiscv: https://github.com/SpinalHDL/VexRiscv

- PicoRV32: https://github.com/YosysHQ/picorv32

- SERV: https://github.com/olofk/serv

- OpenTitan: https://opentitan.org/

- Caliptra: https://www.opencompute.org/projects/caliptra

- Chipyard: https://chipyard.readthedocs.io/

- LiteX: https://github.com/enjoy-digital/litex

- Chisel: https://www.chisel-lang.org/

- SpinalHDL: https://spinalhdl.github.io/SpinalDoc-RTD/

- Amaranth HDL: https://amaranth-lang.org/

- Veryl: https://veryl-lang.org/

- CIRCT (MLIR): https://circt.llvm.org/

- OpenROAD: https://theopenroadproject.org/

- OpenLane: https://github.com/The-OpenROAD-Project/OpenLane

- SkyWater PDK: https://github.com/google/skywater-pdk

- GlobalFoundries 180MCU PDK: https://github.com/google/gf180mcu-pdk

- Tiny Tapeout: https://tinytapeout.com/

- Efabless caravel: https://github.com/efabless/caravel

- BeagleV-Fire: https://beagleboard.org/beaglev-fire

- VisionFive 2: https://www.starfivetech.com/en/site/boards

- Milk-V: https://milkv.io/

- Sipeed LicheePi: https://wiki.sipeed.com/

- Lattice Semiconductor: https://www.latticesemi.com/

- AMD Adaptive Computing: https://www.amd.com/en/products/adaptive-socs-and-fpgas.html

- SiFive: https://www.sifive.com/

- MiSTer FPGA: https://misterfpga.org/