필사 모드: Hardware HDL & Chip Design 2026 — SystemVerilog / Chisel / SpinalHDL / Amaranth / Yosys / Verilator / TinyTapeout / OpenROAD Deep Dive
English1. The 2026 HDL Map — Classic / Scala / Python / Open EDA in Four Continents
If we draw the 2026 HDL and chip-design landscape as a single map, four large continents come into view.
- **Classic HDL** — Verilog (1984, Phil Moorby), SystemVerilog (2005, IEEE 1800), VHDL (1987, IEEE 1076). Industry standard and the lingua franca of every EDA flow.
- **Scala-based HDL** — Chisel (UC Berkeley, 2012), SpinalHDL (2015, a Scala-functional alternative), Bluespec SystemVerilog. One level above for parameterisation, reuse, and code generation.
- **Python-based HDL** — Amaranth (formerly nMigen, 2018, M-Labs / Whitequark), MyHDL (2003, Jan Decaluwe), Migen (2011). Low learning curve, script-friendly.
- **Open EDA flow** — Yosys (Clifford Wolf, 2012), Verilator (Wilson Snyder), Icarus Verilog (Steve Williams), GHDL (Tristan Gingold), nextpnr (YosysHQ), OpenROAD (DARPA IDEA, UC San Diego). And carrying the results into silicon: TinyTapeout, Caravel, the Skywater 130nm PDK.
These four continents communicate. Chisel elaborates to Verilog, Amaranth does too. Yosys reads the synthesisable subset of SystemVerilog, and OpenROAD takes Yosys netlists into placement and routing. **The languages diverge but the back ends increasingly converge.**
This article walks each continent in turn and closes with the Korean and Japanese semiconductor landscape plus a practical guide to "who should learn which HDL."
> Every code example here is current as of May 2026: Verilator 5.x, Yosys 0.40+, OpenROAD 2.0, Chisel 6.x, Amaranth 0.5+.
2. Verilog / SystemVerilog — The Industry Standard That Will Not Move
Where Verilog Stands
Verilog was created in 1984 by Phil Moorby. It became IEEE 1364 in 1995 and was significantly revised in Verilog-2001 and Verilog-2005. Across the ASIC and FPGA industry it is the **de facto common language**.
In 2005 IEEE 1800 brought us **SystemVerilog**, which extended Verilog to cover verification, assertions, and OOP. As of 2026 the current version is IEEE 1800-2023, supported by every major EDA vendor (Cadence, Synopsys, Siemens EDA).
A Simple Counter Example
module counter #(
parameter WIDTH = 8
)(
input wire clk,
input wire rst_n,
input wire enable,
output reg [WIDTH-1:0] count
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
count <= {WIDTH{1'b0}};
else if (enable)
count <= count + 1'b1;
end
endmodule
Rewriting the same code in SystemVerilog lets you use explicit intent constructs like `logic`, `always_ff`, and `always_comb`.
module counter #(
parameter int WIDTH = 8
)(
input logic clk,
input logic rst_n,
input logic enable,
output logic [WIDTH-1:0] count
);
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
count <= '0;
else if (enable)
count <= count + 1'b1;
end
endmodule
`logic` eliminates wire/reg confusion, and `always_ff` makes the synthesiser absolutely clear that "this is a flip-flop." Almost all new RTL in 2026 is SystemVerilog.
The Real Strength of SystemVerilog — UVM and Assertions
SystemVerilogs real win is on the **verification** side. UVM (Universal Verification Methodology, 2011) is an OOP-based testbench framework and an industry verification standard. SystemVerilog Assertion (SVA) makes temporal properties first-class.
// Simple SVA: ack must arrive within 4 cycles after req
property req_ack_p;
@(posedge clk) disable iff (!rst_n)
req |-> ##[1:4] ack;
endproperty
assert property (req_ack_p)
else $error("ack timeout after req");
You cannot express temporal properties like this in Verilog without procedural code. SVA is one of the main reasons SystemVerilog became the industry standard.
3. VHDL — Still Alive in Europe and Defence
VHDL was born in 1987 out of the US Department of Defenses VHSIC programme and standardised as IEEE 1076. It is an Ada-influenced strongly typed, verbose language.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity counter is
generic (
WIDTH : integer := 8
);
port (
clk : in std_logic;
rst_n : in std_logic;
enable : in std_logic;
count : out unsigned(WIDTH-1 downto 0)
);
end entity;
architecture rtl of counter is
signal count_r : unsigned(WIDTH-1 downto 0);
begin
process (clk, rst_n)
begin
if rst_n = '0' then
count_r <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
count_r <= count_r + 1;
end if;
end if;
end process;
count <= count_r;
end architecture;
VHDL is verbose but very explicit. Industry share in 2026 is roughly:
- **US ASIC** — under 5%, almost everything migrated to SystemVerilog.
- **Europe (especially Germany and France)** — around 40%, strong in industrial automation and aerospace.
- **Defence** — much of the US militarys ASIC heritage code is still VHDL (Sentinel, Patriot, and so on).
- **Education** — used as the undergraduate entry language in German and Swiss universities.
A declining but not dead language. The **GHDL** simulator is open source, and the Yosys-GHDL plugin supports synthesis.
4. Chisel — UC Berkeleys Next-Generation RTL Authoring
The Problem Chisel Solves
The weakness of Verilog is **poor meta-programming**. `generate` blocks and `parameter` cannot express complex parameterisation and reuse easily. While building the RISC-V Rocket core in 2012, UC Berkeley designed a new language: **Chisel** (Constructing Hardware in a Scala Embedded Language).
Chisel is a **Scala internal DSL**. You get all of Scalas features (classes, functions, pattern matching, type system) and elaboration produces Verilog or FIRRTL (Flexible Intermediate Representation for RTL).
class Counter(width: Int) extends Module {
val io = IO(new Bundle {
val enable = Input(Bool())
val count = Output(UInt(width.W))
})
val reg = RegInit(0.U(width.W))
when (io.enable) {
reg := reg + 1.U
}
io.count := reg
}
The same counter, but `width` is now a Scala `Int`. You can **run arbitrarily complex Scala computations at elaboration time and generate hardware from the result.**
// Instantiate 16 counters, with special handling on even indices
class MultiCounter extends Module {
val io = IO(new Bundle {
val enable = Input(Bool())
val out = Output(Vec(16, UInt(8.W)))
})
for (i <- 0 until 16) {
val c = Module(new Counter(8))
c.io.enable := io.enable
io.out(i) := c.io.count
if (i % 2 == 0) {
// Special-case even indices
}
}
}
You could write something similar with Verilog `generate`, but the expressiveness is nothing like Scala.
Chisel in the Wild — Rocket, BOOM, Chipyard
All of UC Berkeleys RISC-V cores are written in Chisel.
- **Rocket** — in-order 5-stage scalar RISC-V, capable of booting Linux.
- **BOOM** — Berkeley Out-of-Order Machine, a 4-wide superscalar.
- **Chipyard** — an SoC framework that combines Rocket, BOOM, and peripheral IP.
By 2026 Chisel is **a frequently encountered RTL authoring language** in RISC-V academia and industry. SiFive (a Berkeley spin-out) writes its IP in Chisel.
5. SpinalHDL — Another Strong Option in the Scala Camp
If Chisel is centred around Berkeley and SiFive, **SpinalHDL** is a Scala-based HDL started by Charles Papon in France in 2015. The philosophy is similar but the differences include:
- **Compilation model** — Chisel goes through FIRRTL; SpinalHDL emits Verilog/VHDL directly.
- **Bundle / IO handling** — SpinalHDL treats `master`/`slave` interfaces as first-class.
- **State machines** — a `StateMachine` class is built in.
- **Simulation** — `SpinalSim` is built in and uses Verilator/Icarus as a backend.
class Counter(width: Int) extends Component {
val io = new Bundle {
val enable = in Bool()
val count = out UInt(width bits)
}
val counter = Reg(UInt(width bits)) init(0)
when (io.enable) {
counter := counter + 1
}
io.count := counter
}
object CounterGen extends App {
SpinalVerilog(new Counter(8))
}
SpinalHDL powers real-world cores like VexRiscv (a popular open RISC-V core for FPGAs) and NaxRiscv (out-of-order). The syntax is often called more natural than Chisels, and it has a strong following in European and Japanese hobbyist communities.
6. Bluespec SystemVerilog — Hardware via Atomic Actions
Bluespec is a language grounded in **guarded atomic actions**, researched by Professor Arvind at MIT from the 1990s. Bluespec Inc. commercialised it in the early 2000s, and BSC (the Bluespec Compiler) was open-sourced in 2020.
The key idea is "model hardware as transactions." Each `rule` is atomic, and the scheduler automatically serialises conflicting rules.
module mkCounter (Counter#(8));
Reg#(UInt#(8)) count <- mkReg(0);
method UInt#(8) read = count;
method Action increment if (count < 255);
count <= count + 1;
endmethod
endmodule
`if (count < 255)` is an implicit guard — if the condition is false the rule does not fire. This automatic scheduling is both Bluespecs charm and the source of its learning curve.
Real uses include **MIT research, some IBM ASICs, and the RISC-V Piccolo/Flute cores.** Not mainstream in industry, but still active in academia and the verification community.
7. Amaranth (formerly nMigen) / MyHDL / Migen — The Python Camp
Lineage from Migen to nMigen to Amaranth
- **Migen** (2011, Sébastien Bourdeauducq) — Python for synchronous circuit description. FPGA-friendly with the MiSoC SoC builder.
- **nMigen** (2018, Whitequark / M-Labs) — a redesigned Migen with a cleaner model and better simulator.
- **Amaranth** (2022, nMigen rebrand) — currently active development. The 0.5+ series is the stable line.
from amaranth import *
from amaranth.sim import Simulator
class Counter(Elaboratable):
def __init__(self, width: int):
self.width = width
self.enable = Signal()
self.count = Signal(width)
def elaborate(self, platform):
m = Module()
with m.If(self.enable):
m.d.sync += self.count.eq(self.count + 1)
return m
if __name__ == "__main__":
dut = Counter(8)
sim = Simulator(dut)
sim.add_clock(1e-6)
async def proc(ctx):
ctx.set(dut.enable, 1)
for _ in range(10):
await ctx.tick()
print(ctx.get(dut.count))
sim.add_testbench(proc)
with sim.write_vcd("counter.vcd"):
sim.run()
The advantages of writing RTL in Python are clear — **the standard library, package management, and testing frameworks all carry over**. The drawback is that the synthesis back end is limited to Yosys, and industrial EDA tools in large ASIC flows do not accept Python directly.
MyHDL
MyHDL (2003, Jan Decaluwe) is an older Python HDL. It expresses processes with decorators like `@always_seq` and `@always_comb`.
from myhdl import block, always_seq, Signal, intbv
@block
def counter(clk, rst_n, enable, count):
@always_seq(clk.posedge, reset=rst_n)
def logic():
if enable:
count.next = count + 1
return logic
MyHDL is verbose but extremely clear at the hardware level. It is gradually being displaced by Amaranth, but plenty of legacy projects keep it alive.
8. OpenROAD — The Comprehensive Open EDA Flow
**OpenROAD** (Open Realization Of Autonomous Design) is an open-source EDA flow that started under the DARPA IDEA programme (2018+). UC San Diegos Professor Andrew Kahng leads it.
The flow runs as follows.
1. **Synthesis** — Yosys (SystemVerilog into gate-level netlist).
2. **Floorplanning** — OpenROADs `init_floorplan`, `place_pins`.
3. **Placement** — RePlAce (UCSD).
4. **CTS** (Clock Tree Synthesis) — TritonCTS.
5. **Routing** — TritonRoute / FastRoute.
6. **Static Timing Analysis** — OpenSTA (Parallax).
7. **DRC / LVS** — KLayout, Magic, Netgen.
Combined with open PDKs (Skywater 130nm, GlobalFoundries 180nm), **the entire RTL-to-GDSII flow closes as open source**. This is why in 2026 a student can take an SoC right up to the brink of tape-out on a laptop.
OpenLane — OpenROADs Integration Wrapper
OpenLane is an RTL2GDS flow built on OpenROAD by Efabless. Tcl/Python scripts knit the stages together.
Sketch of an OpenLane run
make mount
./flow.tcl -design my_chip
Drop the PDK, design files, and clock definitions into `config.tcl` or `config.json` and OpenLane carries you from synthesis through placement, routing, and GDSII in a single command. TinyTapeout runs on top of this.
9. Yosys (Clifford Wolf) — The Heart of Open Synthesis
**Yosys** is the open synthesis tool Clifford Wolf (founder of YosysHQ) started in 2012. Small compared with industry-standard synthesisers (e.g. Synopsys Design Compiler) but with key strengths:
- **Supports a synthesisable subset of SystemVerilog** — and even more once you go through UHDM / sv2v.
- **VHDL** — via the GHDL plugin.
- **Multiple back ends** — Verilog, BLIF, JSON (for nextpnr), Liberty timing models.
- **abc integration** — Berkeleys ABC handles logic optimisation.
Minimal Yosys synthesis example
yosys -p "
read_verilog counter.v
synth -top counter
write_json counter.json
"
One line takes Verilog into a gate-level JSON netlist. That JSON feeds directly into nextpnr for placement and routing.
Yosys Limits and Mitigations
Compared with industrial EDA, Yosys is weaker in:
- Synthesis quality on very large designs (tens of thousands of cells and up).
- High-effort logic optimisation.
- Power-aware synthesis (UPF/CPF).
These gaps are partially filled by **Yosys + ABC + designer hints**. For students, hobbyists, and small ASIC flows it is production-ready.
10. Verilator / Icarus Verilog / GHDL — The Open Simulation Trio
Verilator
**Verilator** (Wilson Snyder, Veripool) is a cycle-accurate Verilog / SystemVerilog simulator. It is **not event-driven, but cycle-based** — the RTL model is evaluated on every clock edge. That makes it very fast.
Verilator converts Verilog into C++ or SystemC and compiles it.
verilator -Wall --cc counter.v --exe sim_main.cpp
cd obj_dir
make -j -f Vcounter.mk Vcounter
./Vcounter
`sim_main.cpp` is a C++ testbench.
#include "Vcounter.h"
#include "verilated.h"
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
Vcounter* dut = new Vcounter;
for (int i = 0; i < 100; i++) {
dut->clk = 0; dut->eval();
dut->clk = 1; dut->eval();
}
delete dut;
return 0;
}
Verilator is the de facto standard simulator in the RISC-V community (Rocket / BOOM / CVA6). It runs at **cycle simulation speeds in the tens of MHz** — comparable to commercial industrial simulators.
Icarus Verilog
**Icarus Verilog** (Steve Williams, since 2000) is a more traditional event-driven simulator. Slower than Verilator but with more complete coverage of Verilogs simulation semantics (initial blocks, force/release, and so on). A good fit for small testbenches.
iverilog -o counter_sim counter.v tb_counter.v
vvp counter_sim
GHDL
**GHDL** (Tristan Gingold) is a VHDL simulator. It compiles via an LLVM or GCC back end.
ghdl -a counter.vhd tb_counter.vhd
ghdl -e tb_counter
ghdl -r tb_counter --vcd=wave.vcd
The open standard for the VHDL camp. With the Yosys-GHDL plugin you can take VHDL into Yosys synthesis.
11. nextpnr — The Open Answer for FPGA Placement and Routing
**nextpnr** (YosysHQ) is an FPGA placement and routing tool that builds on reverse-engineered bitstream documentation from Project IceStorm (Clifford Wolf), Project Trellis, Project Apicula, and others.
Supported FPGA families include:
- **Lattice iCE40** — IceStorm-based, fully open.
- **Lattice ECP5** — Trellis-based, fully open.
- **Lattice Nexus** — partial support.
- **Gowin** — Apicula-based.
- **Xilinx 7-Series** — Project XRay-based, experimental.
Path from RTL to an iCE40 FPGA bitstream
yosys -p "synth_ice40 -top top -json design.json" design.v
nextpnr-ice40 --hx8k --json design.json --pcf pins.pcf --asc design.asc
icepack design.asc design.bin
iceprog design.bin # Program the board
This single flow takes RTL into a bitstream and onto a board using nothing but open tools. **A Lattice iCE40 HX8K or ECP5 85K board sits in the 50 to 150 dollar range**, so students can get started cheaply.
Compared with Xilinx / Intel / Microsemi
The open flow versus the commercial vendor flows (AMD Xilinx Vivado, Intel Quartus):
- **iCE40 / ECP5** — the open toolchain is as good as or better than the vendor toolchain.
- **Xilinx 7-Series** — experimental but possible. Vivado remains the industrial standard.
- **Versal / Stratix 10 / Agilex** — commercial-only, no open flow.
The open flow catches up quickly, but **advanced FPGA features like DSP blocks, high-speed SerDes, and HBM memory controllers** stay locked to vendor IP.
12. TinyTapeout — Matt Venns Cheap Path to Real Silicon
**TinyTapeout** is a project the UKs Matt Venn started in 2022. The idea is simple — **gather many small designs onto a single reticle and tape them out together, and the per-designer cost drops to 100 to 300 dollars.**
Each design is tiny — a "tile" is roughly **100 by 100 microns**, around 100 to 500 standard cells. Enough for counters, small state machines, blinking-LED controllers, and small CPUs.
TinyTapeout Generations (as of May 2026)
- **TT01** (2022) — first prototype, Skywater 130nm.
- **TT02 to TT05** (2023 to 2024) — Skywater 130nm, growing participation.
- **TT06 to TT07** (2024 to 2025) — Skywater 130nm stabilises.
- **TT08** (2025) — IHP SG13G2 130nm (Germanys IHP foundry, BiCMOS, open PDK).
- **TT09** (planned for 2026) — two tracks, Skywater or IHP.
User Flow
Write the design in Verilog (or Amaranth, Chisel, SpinalHDL...)
git clone https://github.com/TinyTapeout/tt-template
Write tt_um_yourname.v
Set pin mapping and design name in config.yaml
A GitHub Action runs OpenLane all the way to GDSII
A GitHub Action runs OpenLane to produce GDSII, Matts team aggregates the layouts onto a reticle, and Efabless ships the lot off to Skywater or IHP. **A few months later, an actual chip and PCB arrive in the post.** For a student or hobbyist this is more than a learning exercise — it is real silicon.
13. Skywater 130nm + GlobalFoundries Open PDKs
A PDK (Process Design Kit) is the "how to draw a circuit in this process" manual the foundry hands the designer. It contains the standard-cell library, transistor models, DRC rules, LVS rules, and so on. Traditionally **a strictly NDA-locked asset**.
Skywater 130nm — The First Fully Open PDK
In June 2020, Google and SkyWater (a 130nm foundry near Minneapolis) released the **Skywater Open PDK** under Apache 2.0.
- Standard cells (sky130_fd_sc_hd, hs, ls, ms, hdll, lp)
- I/O cells
- SRAM macros (OpenRAM)
- DRC / LVS rules
This was a historical moment for the open-EDA movement. Anyone could now **carry a 130nm SoC from RTL to GDSII**. 130nm is not bleeding edge — by 2026 the leading edge is 3nm and 2nm — but it is plenty for learning, teaching, and small ASICs.
GlobalFoundries 180nm + 130nm
In 2022 GlobalFoundries (a US fab) opened its **180nm** and **130nm BCDLite** PDKs. A separate alternative to Skywater.
IHP SG13G2 130nm
Germanys IHP opened its **SG13G2 130nm BiCMOS** PDK. BiCMOS combines standard CMOS with BJTs (bipolar junction transistors), useful for analogue and RF. TinyTapeout 08 was the first run to use IHP.
These three PDKs (Skywater 130nm, GF 180nm/130nm, IHP SG13G2) form the foundation of open chip design in 2026.
14. Caravel — Efabless's Open-Chip Harness
**Caravel** (Efabless) is a **standard SoC harness** that wraps a users design. The user fills a roughly 3000 by 3700 micron user_project_wrapper area; surrounding it is Caravels own management SoC (built on PicoRV32), with I/O, SPI, JTAG, and so on.
+-----------------------------------+
| Caravel harness (management SoC) |
| +-----------------------------+ |
| | | |
| | user_project_wrapper | |
| | (designer fills this) | |
| | | |
| +-----------------------------+ |
| PicoRV32, SPI, GPIO, ... |
+-----------------------------------+
Caravel is used in two main flows.
- **OpenMPW** — a Google-sponsored Multi-Project Wafer shuttle. Six rounds at Skywater (2020 to 2023).
- **chipIgnite** — Efabless's commercial shuttle service. Regular tape-outs at about 10,000 dollars.
OpenMPW is over, but Caravel itself lives on. **TinyTapeout operates at a smaller unit; Caravel and chipIgnite work one level up, at an entire reticle slot.**
15. RISC-V Cores — Chipyard / OpenTitan / Ariane-CVA6 / BOOM
The open ISA **RISC-V** sits at the centre of the 2026 chip-design landscape. Academia, industry, and open source all converge on it for a simple reason — **you can build cores freely, with no licence burden.**
Chipyard (UC Berkeley)
Chipyard is Berkeleys RISC-V SoC framework. It bundles:
- **Rocket** — in-order 5-stage scalar.
- **BOOM** — out-of-order superscalar (4 to 10 wide).
- **CVA6 (Ariane)** — PULPs 6-stage in-order.
- **Sodor** — simple core for teaching.
- **NVDLA** — NVIDIA Deep Learning Accelerator integration.
- **Gemmini** — Berkeleys systolic-array DNN accelerator.
// Chipyard config example — Rocket + BOOM + accelerator
class MyBigConfig extends Config(
new chipyard.config.WithSystemBusWidth(128) ++
new boom.common.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig
)
Everything is in Chisel. You can simulate with Verilator and synthesise with Yosys / OpenROAD (for the simpler configurations).
OpenTitan (Google)
**OpenTitan** is Googles open silicon root-of-trust project, hosted by lowRISC. The CPU is **Ibex**, a 4-stage in-order core originally forked from PULPs Zero-riscy. It includes security accelerators, AES, HMAC, KMAC, OTBN (Big Number coprocessor), and a Life Cycle Controller.
OpenTitan has been **taped out as actual industrial silicon root-of-trust chips**. In 2024 the OpenTitan Earl Grey chip went into volume production on GlobalFoundries 22nm — a milestone in open-source ASIC history.
Ariane / CVA6
**Ariane** (ETH Zurich PULP group) is a 6-stage in-order RISC-V core capable of booting Linux. In 2020 it migrated to the OpenHW Group as **CVA6**. Written in SystemVerilog, it is a verified core that has been through industrial verification.
BOOM (Berkeley Out-of-Order Machine)
**BOOM** is the out-of-order RISC-V core Chris Celio built during his PhD. It is written in Chisel and implements the core ideas of x86 OoO designs (e.g. Skylake) — register renaming, reorder buffer, issue queue, ALU and FPU pipelines.
The two pillars of the RISC-V OoO camp in 2026 are **BOOM (Berkeley)** and **XiangShan (Chinese Academy of Sciences ICT, "fragrant mountain")**.
16. HLS — Vitis HLS / Intel oneAPI HLS / MaxCompiler
High-Level Synthesis tools **automatically translate C/C++ or SystemC into RTL**. They excel at heavily parallel dataflow circuits like ML accelerators and image-processing pipelines.
Vitis HLS (AMD/Xilinx)
Vitis HLS is AMD Xilinxs HLS tool. Write a function in C++ and out comes a Verilog module.
// Vitis HLS example — 8-tap FIR filter
#include "ap_int.h"
void fir(ap_int<16> in, ap_int<16> *out) {
static ap_int<16> shift_reg[8] = {0};
static const ap_int<16> coeffs[8] = {1, 2, 3, 4, 4, 3, 2, 1};
shift_reg[0] = in;
ap_int<32> sum = 0;
for (int i = 0; i < 8; i++) {
#pragma HLS UNROLL
sum += shift_reg[i] * coeffs[i];
}
for (int i = 7; i > 0; i--) {
#pragma HLS UNROLL
shift_reg[i] = shift_reg[i-1];
}
*out = sum.range(31, 16);
}
`#pragma HLS UNROLL` tells the synthesiser to "unroll this loop into parallel hardware."
Intel oneAPI HLS
The Intel camp (now spun back out as Altera) supplies oneAPI-based HLS. SYCL/DPC++-based.
MaxCompiler (Maxeler / Groq)
MaxCompiler is an HLS dedicated to dataflow computing. Originally from Maxeler, it was acquired by Groq in 2022. You describe a dataflow graph in **MaxJ** (a Java-based DSL). It has been used for FPGA accelerators in finance and scientific computing.
HLS is faster than writing RTL by hand, but **the best PPA (Performance / Power / Area) generally still comes from RTL**. For ML and DSP dataflow, HLS keeps gaining industrial share.
17. Korean Semiconductors — Samsung / SK hynix / LG / KAIST
Korea is a semiconductor powerhouse, but on the HDL surface it is **conservative**. Industrial flows centre on SystemVerilog plus Synopsys/Cadence plus in-house verification infrastructure.
Samsung Electronics Foundry / Memory
- **Foundry (Foundry Business)** — developing 4nm GAA, 3nm GAA, 2nm. Receives customer RTL, so the HDL is SystemVerilog or Verilog.
- **Memory (Memory Business)** — DRAM and NAND. Memory controllers and PHYs are highly polished SystemVerilog. UVM testbenches are the industry standard.
- **LSI** — Exynos AP and SoC integration. ARM Cortex with in-house GPU and NPU. SystemVerilog plus UPF (power intent).
Samsung Foundry runs **SAFE (Samsung Advanced Foundry Ecosystem)**, an EDA-partner programme that validates Cadence, Synopsys, and Siemens EDA tools against the Samsung PDK.
SK hynix
SK hynix is a DRAM, NAND, and HBM leader, sitting at the top of HBM3E and HBM4 development. PHY and controller HDL is proprietary, but the standard is SystemVerilog plus UVM.
In 2024 and 2025, SK hynix became the main supplier of HBM for NVIDIAs H100, H200, B100, and B200 — raising Korean semiconductors place in the AI value chain.
LG (Autonomous Driving / Automotive Semiconductors)
LG Chem, LG Electronics, and LG Innotek develop in-house ASICs for autonomous ECUs and automotive vision ICs. Automotive certification (AEC-Q100, ISO 26262) is essential, so the HDL flow is SystemVerilog plus formal verification.
KAIST and Academia
KAISTs Department of Electrical Engineering teaches RISC-V cores at both undergraduate and graduate levels. Some courses cover **both Chipyard and SpinalHDL**. Seoul National University, POSTECH, and UNIST also run RISC-V SoC design courses.
For Korean students, **submitting to TinyTapeout is becoming increasingly common** — an undergraduate capstone project where a small slice of silicon actually becomes a chip.
18. Japanese Semiconductors — Sony / NEC / Renesas / Toshiba / Rapidus 2nm
Japanese semiconductors retreated from their 1980s peak but remain dominant in **image sensors, automotive, MCUs, and memory**. And the **Rapidus** project, launched in 2022, is the centerpiece of Japan's semiconductor revival.
Sony Semiconductor Solutions
Sony is **the world number one in CMOS image sensors** (around 50% market share). Most of the main camera sensors in iPhones and Android flagships are Sony. CIS chip RTL flows through an in-house SystemVerilog + UVM pipeline.
NEC / Renesas / Toshiba
- **NEC** — has largely exited semiconductors, with NEC Electronics merged into Renesas Electronics.
- **Renesas** — automotive MCUs and ARM-based SoCs. The R-Car (automotive SoC) series is central.
- **Toshiba (Kioxia, NAND)** — NAND flash memory, spun off as Kioxia.
- **ROHM, Rohm Semiconductor** — analogue and power ICs.
These houses also use SystemVerilog + UVM. Japans reliability culture invests heavily in verification — formal verification, UVM coverage, and post-silicon validation all included.
Rapidus — The 2nm GAA Challenge
**Rapidus** is the advanced foundry the Japanese government helped form in August 2022. Investors include Toyota, Sony, NTT, NEC, SoftBank, Denso, Kioxia, and Mitsubishi UFJ. In partnership with IBM, it is developing the **2nm GAA (Gate-All-Around)** process. The fab is being built in Chitose, Hokkaido.
Targets: 2nm prototypes in 2025, full production around 2026 to 2027. Success would put Japan in the top three advanced foundries alongside TSMC and Samsung. Several variables remain — Japans EUV infrastructure, talent pipeline, and customer base.
Japanese students and engineers commonly start semiconductor careers via **internships at Renesas, Sony, or Rapidus**, or at equipment and photomask companies like Toppan Photomask, Tokyo Electron, Disco, and Lasertec.
19. Who Should Learn Which HDL
Aiming for Industrial ASIC
- **SystemVerilog** (mandatory) — industry standard, including UVM.
- **VHDL** (optional) — useful for European hiring.
- **Tcl** — the scripting language of every EDA tool.
- **Python** — environment automation and result analysis.
Aiming for FPGA Engineering
- **SystemVerilog or VHDL** — Vivado / Quartus accept both.
- **Vitis HLS or Intel HLS** — for DSP / ML acceleration circuits.
- **Yosys + nextpnr** — start with iCE40 / ECP5 boards.
- **Verilator** — for fast simulation.
RISC-V / Open Chips / Academia
- **Chisel** (or SpinalHDL) — required to read Chipyard or BOOM code.
- **SystemVerilog** — CVA6 and OpenTitan are written in SV.
- **Amaranth** — great for quickly hacking small SoCs.
- **Verilator + Yosys + OpenROAD + Skywater 130nm** — the entire RTL-to-GDSII flow.
- **TinyTapeout** — strongly recommended for your first silicon experience.
Hobbyists / Students
1. Get an **iCE40 HX8K board** (around 50 dollars) or a **ULX3S** (around 130 dollars).
2. Write RTL in **Amaranth or Chisel**, synthesise with Yosys + nextpnr, and burn it to the board.
3. Read one RISC-V core (PicoRV32, NEORV32, VexRiscv) cover to cover.
4. Submit a small design to **TinyTapeout** once — between 100 and 300 dollars for genuine silicon experience.
Verification Specialists
- **SystemVerilog + UVM** — the industry standard verification language.
- **SVA (Assertion)** — the entry point to formal verification.
- **cocotb** (Python) — a Python testbench framework that pairs with Verilator / Icarus, gaining traction.
- **SymbiYosys** — open formal verification on top of Yosys.
20. References
- IEEE 1800-2023 — [SystemVerilog Standard](https://standards.ieee.org/ieee/1800/7743/)
- IEEE 1076 — [VHDL Standard](https://standards.ieee.org/ieee/1076/10800/)
- Chisel — [chisel-lang.org](https://www.chisel-lang.org/)
- Chisel GitHub — [github.com/chipsalliance/chisel](https://github.com/chipsalliance/chisel)
- SpinalHDL — [spinalhdl.github.io](https://spinalhdl.github.io/SpinalDoc-RTD/)
- SpinalHDL GitHub — [github.com/SpinalHDL/SpinalHDL](https://github.com/SpinalHDL/SpinalHDL)
- Bluespec Compiler (BSC) — [github.com/B-Lang-org/bsc](https://github.com/B-Lang-org/bsc)
- Amaranth — [amaranth-lang.org](https://amaranth-lang.org/)
- Amaranth GitHub — [github.com/amaranth-lang/amaranth](https://github.com/amaranth-lang/amaranth)
- MyHDL — [myhdl.org](https://www.myhdl.org/)
- Migen — [github.com/m-labs/migen](https://github.com/m-labs/migen)
- Yosys — [yosyshq.net/yosys](https://yosyshq.net/yosys/)
- Yosys GitHub — [github.com/YosysHQ/yosys](https://github.com/YosysHQ/yosys)
- Verilator — [veripool.org/verilator](https://www.veripool.org/verilator/)
- Verilator GitHub — [github.com/verilator/verilator](https://github.com/verilator/verilator)
- Icarus Verilog — [steveicarus.github.io/iverilog](https://steveicarus.github.io/iverilog/)
- GHDL — [ghdl.github.io/ghdl](https://ghdl.github.io/ghdl/)
- nextpnr — [github.com/YosysHQ/nextpnr](https://github.com/YosysHQ/nextpnr)
- Project IceStorm — [clifford.at/icestorm](http://www.clifford.at/icestorm/)
- Project Trellis — [github.com/YosysHQ/prjtrellis](https://github.com/YosysHQ/prjtrellis)
- OpenROAD — [theopenroadproject.org](https://theopenroadproject.org/)
- OpenROAD GitHub — [github.com/The-OpenROAD-Project/OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD)
- OpenLane — [github.com/The-OpenROAD-Project/OpenLane](https://github.com/The-OpenROAD-Project/OpenLane)
- TinyTapeout — [tinytapeout.com](https://tinytapeout.com/)
- TinyTapeout GitHub — [github.com/TinyTapeout](https://github.com/TinyTapeout)
- Skywater 130nm PDK — [github.com/google/skywater-pdk](https://github.com/google/skywater-pdk)
- Open MPW (Google) — [efabless.com/openmpw](https://efabless.com/open_shuttle_program)
- Caravel — [github.com/efabless/caravel](https://github.com/efabless/caravel)
- Efabless — [efabless.com](https://efabless.com/)
- chipIgnite — [efabless.com/chipignite](https://efabless.com/chipignite)
- GlobalFoundries Open PDK — [github.com/google/gf180mcu-pdk](https://github.com/google/gf180mcu-pdk)
- IHP SG13G2 — [github.com/IHP-GmbH/IHP-Open-PDK](https://github.com/IHP-GmbH/IHP-Open-PDK)
- Chipyard — [chipyard.readthedocs.io](https://chipyard.readthedocs.io/)
- Chipyard GitHub — [github.com/ucb-bar/chipyard](https://github.com/ucb-bar/chipyard)
- Rocket Chip — [github.com/chipsalliance/rocket-chip](https://github.com/chipsalliance/rocket-chip)
- BOOM (Berkeley Out-of-Order Machine) — [github.com/riscv-boom/riscv-boom](https://github.com/riscv-boom/riscv-boom)
- OpenTitan — [opentitan.org](https://opentitan.org/)
- lowRISC — [lowrisc.org](https://lowrisc.org/)
- Ibex — [github.com/lowRISC/ibex](https://github.com/lowRISC/ibex)
- CVA6 (Ariane) — [github.com/openhwgroup/cva6](https://github.com/openhwgroup/cva6)
- VexRiscv — [github.com/SpinalHDL/VexRiscv](https://github.com/SpinalHDL/VexRiscv)
- PicoRV32 — [github.com/YosysHQ/picorv32](https://github.com/YosysHQ/picorv32)
- NEORV32 — [github.com/stnolting/neorv32](https://github.com/stnolting/neorv32)
- XiangShan — [github.com/OpenXiangShan/XiangShan](https://github.com/OpenXiangShan/XiangShan)
- Vitis HLS — [docs.amd.com/r/en-US/ug1399-vitis-hls](https://docs.amd.com/r/en-US/ug1399-vitis-hls)
- Intel HLS — [intel.com/content/www/us/en/software-kit/highlevel-synthesis-compiler](https://www.intel.com/content/www/us/en/software-kit/highlevel-synthesis-compiler.html)
- SymbiYosys — [github.com/YosysHQ/sby](https://github.com/YosysHQ/sby)
- cocotb — [cocotb.org](https://www.cocotb.org/)
- RISC-V International — [riscv.org](https://riscv.org/)
- Samsung Foundry — [samsungfoundry.com](https://semiconductor.samsung.com/foundry/)
- SK hynix — [skhynix.com](https://www.skhynix.com/)
- Renesas — [renesas.com](https://www.renesas.com/)
- Sony Semiconductor — [sony-semicon.com](https://www.sony-semicon.com/)
- Rapidus — [rapidus.inc](https://www.rapidus.inc/)
- Matt Venn (TinyTapeout founder) — [mattvenn.net](https://mattvenn.net/)
- Clifford Wolf (Yosys founder) — [clifford.at](http://www.clifford.at/)
현재 단락 (1/435)
If we draw the 2026 HDL and chip-design landscape as a single map, four large continents come into v...