https://www.youngju.dev/blog 천천히 올바르게. AI Researcher & DevOps Engineer Youngju's tech blog. GPU/CUDA, LLM, MLOps, Kubernetes AI workloads, distributed training, and data engineering. ko fjvbn2003@gmail.com (Youngju Kim) fjvbn2003@gmail.com (Youngju Kim) Sat, 16 May 2026 00:00:00 GMT https://www.youngju.dev/blog/culture/2026-05-16-hardware-hdl-chip-design-2026-systemverilog-chisel-spinalhdl-amaranth-yosys-verilator-tinytapeout-deep-dive.en https://www.youngju.dev/blog/culture/2026-05-16-hardware-hdl-chip-design-2026-systemverilog-chisel-spinalhdl-amaranth-yosys-verilator-tinytapeout-deep-dive.en The hardware description language (HDL) and chip-design landscape in 2026 is multi-layered. The industry standard is still Verilog/SystemVerilog, but UC Berkeleys Chisel has become the de facto choice for RISC-V cores like BOOM and Rocket, while SpinalHDL and Amaranth (formerly nMigen) hold strong positions in the Scala/Python camps. On the open-EDA side, Clifford Wolfs Yosys, Verilator, nextpnr, and OpenROAD form a complete open toolchain, and open PDKs like Skywater 130nm and GlobalFoundries 130nm/180nm have opened the path to real silicon. Matt Venns TinyTapeout has now run through eight generations (2024 IHP/SkyWater), letting students and hobbyists tape out their own chips. The RISC-V core ecosystem is exploding with Chipyard, OpenTitan (Google), Ariane/CVA6 (PULP), and BOOM (Berkeley), while Korean and Japanese foundries / memory houses — Samsung, SK hynix, Sony, NEC, Renesas, Toshiba, Rapidus — keep their internal HDL flows while gradually adopting open tools. This article walks through every piece. Sat, 16 May 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) hdlhardware-designchip-designverilogsystemverilogvhdlchiselspinalhdlbluespecamaranthnmigenmyhdlopenroadyosysverilatoricarus-verilogghdlnextpnrtinytapeoutskywater-pdkcaravelefablesslattice-ecp5ice40risc-vchipyardopentitanboomrapidus2026deep-diveenglish https://www.youngju.dev/blog/culture/2026-05-16-hardware-hdl-chip-design-2026-systemverilog-chisel-spinalhdl-amaranth-yosys-verilator-tinytapeout-deep-dive.ja https://www.youngju.dev/blog/culture/2026-05-16-hardware-hdl-chip-design-2026-systemverilog-chisel-spinalhdl-amaranth-yosys-verilator-tinytapeout-deep-dive.ja 2026年のハードウェア記述言語（HDL）とチップ設計の風景は多層的だ。業界標準は依然としてVerilog/SystemVerilogだが、UC BerkeleyのChiselはBOOMやRocketといったRISC-Vコアの事実上の標準となり、SpinalHDLとAmaranth（旧nMigen）はScala/Python陣営の強力な代替として地位を確立した。オープンEDAではClifford WolfのYosys、Verilator、nextpnr、OpenROADが完全なオープンツールチェーンを形成し、Skywater 130nmやGlobalFoundries 130nm/180nmといったオープンPDKが実シリコンへの道を開いた。Matt VennのTinyTapeoutはすでに第8世代（2024年のIHP/SkyWater）まで進み、学生や趣味家でもチップを作れるようになった。RISC-Vコア生態系はChipyard、OpenTitan（Google）、Ariane/CVA6（PULP）、BOOM（Berkeley）で爆発的に拡大し、サムスン、SKハイニックス、ソニー、NEC、ルネサス、東芝、ラピダスといった日韓のファウンドリ・メモリ各社は自社のHDLフローを維持しつつオープンツールを徐々に取り入れている。本記事はこれら全てのピースを一つずつ解きほぐす。 Sat, 16 May 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) hdlhardware-designchip-designverilogsystemverilogvhdlchiselspinalhdlbluespecamaranthnmigenmyhdlopenroadyosysverilatoricarus-verilogghdlnextpnrtinytapeoutskywater-pdkcaravelefablesslattice-ecp5ice40risc-vchipyardopentitanboomrapidus2026deep-dive日本語 https://www.youngju.dev/blog/culture/2026-05-16-hardware-hdl-chip-design-2026-systemverilog-chisel-spinalhdl-amaranth-yosys-verilator-tinytapeout-deep-dive https://www.youngju.dev/blog/culture/2026-05-16-hardware-hdl-chip-design-2026-systemverilog-chisel-spinalhdl-amaranth-yosys-verilator-tinytapeout-deep-dive 2026년의 하드웨어 기술 언어(HDL)와 칩 설계 풍경은 다층적이다. 산업 표준은 여전히 Verilog/SystemVerilog지만, UC Berkeley의 Chisel은 BOOM과 Rocket 같은 RISC-V 코어의 표준이 되었고, SpinalHDL과 Amaranth(구 nMigen)는 Scala/Python 진영의 강력한 대안으로 자리잡았다. 오픈 EDA 쪽은 Clifford Wolf의 Yosys, Verilator, nextpnr, OpenROAD가 완전한 오픈 툴체인을 형성했고, Skywater 130nm와 GlobalFoundries 130nm/180nm 같은 오픈 PDK는 실제 실리콘으로 가는 길을 열었다. Matt Venn의 TinyTapeout은 이미 8세대(2024 IHP/SkyWater)를 거치며 학생과 취미가도 칩을 만들 수 있게 했다. RISC-V 코어 생태계는 Chipyard, OpenTitan(Google), Ariane/CVA6(PULP), BOOM(Berkeley)로 폭발하고 있고, 삼성/하이닉스/Sony/NEC/Renesas/Toshiba/Rapidus 같은 한·일 파운드리·메모리 업체들은 자체 HDL 흐름을 그대로 유지하면서 오픈 툴을 점진적으로 받아들이는 중이다. 이 글은 이 모든 조각을 한 장씩 풀어낸다. Sat, 16 May 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) hdlhardware-designchip-designverilogsystemverilogvhdlchiselspinalhdlbluespecamaranthnmigenmyhdlopenroadyosysverilatoricarus-verilogghdlnextpnrtinytapeoutskywater-pdkcaravelefablesslattice-ecp5ice40risc-vchipyardopentitanboomrapidus2026deep-dive