https://www.youngju.dev/blog 천천히 올바르게. AI Researcher & DevOps Engineer Youngju's tech blog. GPU/CUDA, LLM, MLOps, Kubernetes AI workloads, distributed training, and data engineering. ko fjvbn2003@gmail.com (Youngju Kim) fjvbn2003@gmail.com (Youngju Kim) Tue, 16 Jun 2026 00:00:00 GMT https://www.youngju.dev/blog/gpu-cuda/2026-06-16-groq-sambanova-inference-chips.en https://www.youngju.dev/blog/gpu-cuda/2026-06-16-groq-sambanova-inference-chips.en A deep look at the working principles of two chips that bet everything on inference rather than training: the Groq LPU and the SambaNova RDU. We cover how deterministic execution and compiler scheduling, plus reconfigurable dataflow, produce low latency, and where they win and lose against GPUs. Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) groqsambanovainferenceai-hardwarelpudataflow https://www.youngju.dev/blog/gpu-cuda/2026-06-16-groq-sambanova-inference-chips.ja https://www.youngju.dev/blog/gpu-cuda/2026-06-16-groq-sambanova-inference-chips.ja 学習ではなく推論にすべてを賭けた2つのチップ、Groq LPU と SambaNova RDU の動作原理を深く覗き込みます。決定的実行とコンパイラスケジューリング、reconfigurable dataflow がどう低遅延を生むか、そしてGPUに対しどこで勝ちどこで負けるかを整理します。 Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) groqsambanovainferenceai-hardwarelpudataflow https://www.youngju.dev/blog/gpu-cuda/2026-06-16-groq-sambanova-inference-chips https://www.youngju.dev/blog/gpu-cuda/2026-06-16-groq-sambanova-inference-chips 학습이 아니라 추론에 모든 것을 건 두 칩, Groq LPU와 SambaNova RDU의 동작 원리를 깊게 들여다봅니다. 결정적 실행과 컴파일러 스케줄링, reconfigurable dataflow가 어떻게 낮은 지연을 만들어내는지, 그리고 GPU 대비 어디서 이기고 어디서 지는지 정리합니다. Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) groqsambanovainferenceai-hardwarelpudataflow https://www.youngju.dev/blog/gpu-cuda/2026-06-16-inference-hardware-quantization-sparsity-dataflow.en https://www.youngju.dev/blog/gpu-cuda/2026-06-16-inference-hardware-quantization-sparsity-dataflow.en We break down the cost structure of inference through the memory-wall lens, then connect quantization (INT8/FP8/FP4), structured sparsity (2:4), dataflow architectures, operator fusion, batching and KV caching into one picture of hardware-software co-design. Reflects the 2026 reality of Blackwell FP4 and the Vera Rubin trajectory, with practical guidance for shipping fast inference. Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) inferencequantizationsparsitydataflowgpuhardwareoptimization https://www.youngju.dev/blog/gpu-cuda/2026-06-16-inference-hardware-quantization-sparsity-dataflow.ja https://www.youngju.dev/blog/gpu-cuda/2026-06-16-inference-hardware-quantization-sparsity-dataflow.ja 推論コストの構造をメモリウォールの観点から解きほぐし、量子化(INT8/FP8/FP4)、構造化スパース性(2:4)、dataflow アーキテクチャ、演算子融合、バッチングと KV キャッシュまでをハードウェアとソフトウェアの協調設計として一枚の絵にまとめます。2026 年の Blackwell FP4 と Vera Rubin の流れを反映し、実務での適用ポイントを示します。 Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) inferencequantizationsparsitydataflowgpuhardwareoptimization https://www.youngju.dev/blog/gpu-cuda/2026-06-16-inference-hardware-quantization-sparsity-dataflow https://www.youngju.dev/blog/gpu-cuda/2026-06-16-inference-hardware-quantization-sparsity-dataflow 추론 비용의 구조를 메모리 월 관점에서 풀어내고, 양자화(INT8/FP8/FP4)와 구조적 희소성(2:4), dataflow 아키텍처, 연산자 융합, 배칭과 KV 캐시까지 하드웨어-소프트웨어 공동설계의 큰 그림을 정리합니다. 2026년 Blackwell FP4와 Vera Rubin 흐름을 반영해 실무 적용 포인트를 짚습니다. Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) inferencequantizationsparsitydataflowgpuhardwareoptimization https://www.youngju.dev/blog/gpu-cuda/2026-06-16-systolic-array-dataflow-architecture.en https://www.youngju.dev/blog/gpu-cuda/2026-06-16-systolic-array-dataflow-architecture.en A deep dive into the systolic array, the structure that lets AI accelerators run matrix multiplication efficiently, complete with ASCII diagrams. We walk through dataflow strategies like weight-stationary and output-stationary, data reuse and energy, the comparison with tensor cores, and compiler mapping — the core principles that power the TPU. Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) gpu-cudasystolic-arraydataflowtpuai-hardwarematrix-multiplyaccelerator https://www.youngju.dev/blog/gpu-cuda/2026-06-16-systolic-array-dataflow-architecture.ja https://www.youngju.dev/blog/gpu-cuda/2026-06-16-systolic-array-dataflow-architecture.ja AIアクセラレータの中核演算である行列積を効率的に処理するシストリックアレイの動作原理を、ASCII図とともに深く掘り下げます。weight-stationaryやoutput-stationaryといったデータフロー戦略、データ再利用とエネルギー、テンソルコアとの比較、コンパイラのマッピングまで、TPUの心臓原理を整理します。 Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) gpu-cudasystolic-arraydataflowtpuai-hardwarematrix-multiplyaccelerator https://www.youngju.dev/blog/gpu-cuda/2026-06-16-systolic-array-dataflow-architecture https://www.youngju.dev/blog/gpu-cuda/2026-06-16-systolic-array-dataflow-architecture AI 가속기의 핵심 연산인 행렬곱을 효율적으로 처리하는 systolic array의 동작 원리를 ASCII 다이어그램과 함께 깊이 파헤칩니다. weight-stationary와 output-stationary 같은 dataflow 전략, 데이터 재사용과 에너지, 텐서코어와의 비교, 컴파일러 매핑까지 TPU의 심장 원리를 정리합니다. Tue, 16 Jun 2026 00:00:00 GMT fjvbn2003@gmail.com (Youngju Kim) gpu-cudasystolic-arraydataflowtpuai-hardwarematrix-multiplyaccelerator