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Split View: 전자회로 완전 가이드: 다이오드부터 연산증폭기까지

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전자회로 완전 가이드: 다이오드부터 연산증폭기까지

전자회로 완전 가이드: 다이오드부터 연산증폭기까지

전기/전자공학의 핵심인 아날로그 전자회로를 체계적으로 정리합니다. 회로 이론 기초부터 시작해 반도체 소자, 증폭기 설계, 필터, 전원 공급 장치까지 실습 예제와 함께 다룹니다.


1. 회로 이론 기초

키르히호프의 법칙

키르히호프 전압 법칙 (KVL): 임의의 폐루프에서 전압의 대수합은 0입니다.

k=1nVk=0\sum_{k=1}^{n} V_k = 0

키르히호프 전류 법칙 (KCL): 임의의 노드에서 유입/유출 전류의 합은 0입니다.

k=1nIk=0\sum_{k=1}^{n} I_k = 0

import numpy as np

# KVL/KCL 노드 해석 예시
# 회로: V1=12V, R1=1kΩ, R2=2kΩ, R3=3kΩ
# 노드 전압법으로 V_node 계산

G = np.array([
    [1/1e3 + 1/2e3, -1/2e3],
    [-1/2e3, 1/2e3 + 1/3e3]
])
I = np.array([12/1e3, 0])
V = np.linalg.solve(G, I)
print(f"노드 전압: V1={V[0]:.3f}V, V2={V[1]:.3f}V")

테브난/노턴 등가 회로

임의의 선형 회로는 테브난 전압 VthV_{th}와 테브난 저항 RthR_{th}의 직렬 조합으로 단순화할 수 있습니다. 노턴 등가는 IN=Vth/RthI_N = V_{th}/R_{th}RN=RthR_N = R_{th}의 병렬 조합입니다.

최대 전력 전달: 부하 저항 RL=RthR_L = R_{th}일 때 최대 전력이 전달됩니다.

Pmax=Vth24RthP_{max} = \frac{V_{th}^2}{4R_{th}}

AC 회로와 페이저 분석

임피던스 표현:

  • 저항: ZR=RZ_R = R
  • 인덕터: ZL=jωLZ_L = j\omega L
  • 커패시터: ZC=1jωCZ_C = \frac{1}{j\omega C}

전달 함수 (Transfer Function)와 보드 선도(Bode Plot)는 주파수 응답 분석의 핵심 도구입니다.


2. 다이오드 (Diode)

p-n 접합의 물리적 동작

p형 반도체(정공 다수 캐리어)와 n형 반도체(전자 다수 캐리어)가 접합하면 공핍층(Depletion Region)이 형성됩니다. 순방향 바이어스 시 공핍층이 좁아져 전류가 흐르고, 역방향 바이어스 시 공핍층이 넓어져 전류가 차단됩니다.

쇼클리 다이오드 방정식

ID=IS(eVD/nVT1)I_D = I_S\left(e^{V_D / nV_T} - 1\right)

여기서:

  • ISI_S: 역포화 전류 (약 101410^{-14} A 수준)
  • nn: 이상 인자 (이상적: 1, 실제: 1~2)
  • VT=kT/qV_T = kT/q: 열전압 (실온 25도에서 약 26 mV)
import numpy as np
import matplotlib.pyplot as plt

# 다이오드 I-V 특성 곡선
V = np.linspace(-0.5, 0.8, 1000)
IS = 1e-14      # 역포화 전류
n = 1.0         # 이상 인자
VT = 0.02585    # 열전압 (25도)

ID = IS * (np.exp(V / (n * VT)) - 1)
ID_clipped = np.clip(ID, -1e-12, 0.1)  # 가시성을 위해 클리핑

plt.figure(figsize=(8, 5))
plt.plot(V, ID_clipped * 1000, 'b-', linewidth=2)
plt.axhline(y=0, color='k', linewidth=0.5)
plt.axvline(x=0, color='k', linewidth=0.5)
plt.xlabel('전압 V_D (V)')
plt.ylabel('전류 I_D (mA)')
plt.title('다이오드 I-V 특성 곡선')
plt.grid(True, alpha=0.3)
plt.xlim(-0.5, 0.8)
plt.ylim(-0.01, 0.1)
plt.show()

정류 회로

반파 정류: 다이오드 1개로 교류의 한 방향만 통과시킵니다. 출력 평균 전압은 Vavg=Vm/πV_{avg} = V_m / \pi입니다.

전파 정류 (브리지 정류): 4개의 다이오드로 교류의 양 방향을 정류합니다. 출력 평균 전압은 Vavg=2Vm/πV_{avg} = 2V_m / \pi입니다.

제너 다이오드

역방향 항복 전압을 이용한 전압 기준 소자입니다. 제너 전압 VZV_Z에서 동작하며 간단한 전압 안정화 회로에 사용됩니다.

Vout=VZ,RS=VinVZIZ+ILV_{out} = V_Z, \quad R_S = \frac{V_{in} - V_Z}{I_Z + I_L}


3. BJT 트랜지스터

구조와 동작 모드

BJT(Bipolar Junction Transistor)는 이미터(E), 베이스(B), 컬렉터(C) 세 단자로 구성됩니다.

동작 모드B-E 접합B-C 접합용도
차단 (Cutoff)역방향역방향스위치 OFF
활성 (Active)순방향역방향증폭기
포화 (Saturation)순방향순방향스위치 ON

활성 영역에서: IC=βIB=hFEIBI_C = \beta I_B = h_{FE} I_B

DC 바이어스 설계

가장 안정적인 전압 분배기 바이어스 방식:

VB=VCCR2R1+R2V_B = V_{CC} \cdot \frac{R_2}{R_1 + R_2} VE=VBVBEVB0.7 VV_E = V_B - V_{BE} \approx V_B - 0.7\text{ V} ICIE=VEREI_C \approx I_E = \frac{V_E}{R_E}

소신호 등가 회로 (하이브리드-π 모델)

핵심 파라미터:

  • gm=IC/VTg_m = I_C / V_T: 트랜스컨덕턴스
  • rπ=β/gmr_\pi = \beta / g_m: 입력 저항
  • ro=VA/ICr_o = V_A / I_C: 출력 저항 (Early 효과)

증폭기 구성 비교

구성전압 이득전류 이득입력 임피던스출력 임피던스용도
공통 이미터 (CE)높음 (반전)높음중간중간범용 증폭
공통 컬렉터 (CC)~1높음높음낮음버퍼, 임피던스 변환
공통 베이스 (CB)높음~1낮음높음고주파 증폭

공통 이미터 증폭기 전압 이득:

Av=gm(RCro)RCreA_v = -g_m (R_C \| r_o) \approx -\frac{R_C}{r_e}


4. MOSFET

동작 원리와 영역

MOSFET(Metal-Oxide-Semiconductor FET)은 게이트(G), 드레인(D), 소스(S), 기판(B) 네 단자 소자입니다. n-채널 MOSFET 기준:

차단 영역: VGS<VthV_{GS} < V_{th}ID0I_D \approx 0

선형(오믹) 영역: VGS>VthV_{GS} > V_{th}, VDS<VGSVthV_{DS} < V_{GS} - V_{th}

ID=μnCoxWL[(VGSVth)VDSVDS22]I_D = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right]

포화 영역: VDSVGSVthV_{DS} \geq V_{GS} - V_{th}

ID=12μnCoxWL(VGSVth)2(1+λVDS)I_D = \frac{1}{2}\mu_n C_{ox} \frac{W}{L}(V_{GS} - V_{th})^2 (1 + \lambda V_{DS})

소신호 파라미터

  • gm=2μnCox(W/L)IDg_m = \sqrt{2\mu_n C_{ox}(W/L)I_D}: 트랜스컨덕턴스
  • ro=1/(λID)r_o = 1/(\lambda I_D): 출력 저항

CMOS 인버터

디지털 논리의 기본 게이트. PMOS와 NMOS의 상보적 동작으로 정적 전력 소모가 거의 없습니다. 스위칭 에너지: E=CVDD2E = CV_{DD}^2


5. 연산증폭기 (Op-Amp)

이상적 Op-Amp 특성

파라미터이상적 값실제 값 예시 (LM741)
개루프 이득 AOLA_{OL}무한대~200,000
입력 임피던스 RinR_{in}무한대~2 MΩ
출력 임피던스 RoutR_{out}0~75 Ω
대역폭무한대~1 MHz (GBW)
CMRR무한대~90 dB

가상 단락 (Virtual Short): 부피드백 적용 시 두 입력 단자 전압이 동일 → V+=VV^+ = V^-

가상 개방 (Virtual Open): 이상적 입력 임피던스 무한대 → 입력 단자로 전류 유입 없음

기본 Op-Amp 회로

반전 증폭기:

Av=RfR1A_v = -\frac{R_f}{R_1}

비반전 증폭기:

Av=1+RfR1A_v = 1 + \frac{R_f}{R_1}

차동 증폭기 (CMRR이 높을 때):

Vout=RfR1(V2V1)V_{out} = \frac{R_f}{R_1}(V_2 - V_1)

적분기 (밀러 적분기):

Vout(t)=1R1CVin(t)dtV_{out}(t) = -\frac{1}{R_1 C} \int V_{in}(t)\, dt

미분기:

Vout(t)=RfCdVindtV_{out}(t) = -R_f C \frac{dV_{in}}{dt}

import numpy as np
import matplotlib.pyplot as plt

# 반전 증폭기 주파수 응답 시뮬레이션
f = np.logspace(1, 7, 1000)  # 10Hz ~ 10MHz
GBW = 1e6  # 1MHz 이득-대역폭 적
R1, Rf = 1e3, 10e3

Av_ideal = -Rf / R1  # 이상적 이득 = -10

# 개루프 이득 (단순 1차 모델)
A_open = GBW / (1j * f)

# 폐루프 이득
beta = R1 / (R1 + Rf)
Av_closed = A_open / (1 + A_open * beta)

plt.figure(figsize=(10, 6))
plt.subplot(2, 1, 1)
plt.semilogx(f, 20*np.log10(np.abs(Av_closed)), 'b-', linewidth=2, label='실제 이득')
plt.axhline(y=20*np.log10(abs(Av_ideal)), color='r', linestyle='--', label='이상적 이득 (20dB)')
plt.ylabel('이득 (dB)')
plt.title('반전 증폭기 주파수 응답 (GBW=1MHz, Av=-10)')
plt.legend()
plt.grid(True, alpha=0.3)

plt.subplot(2, 1, 2)
plt.semilogx(f, np.angle(Av_closed, deg=True), 'g-', linewidth=2)
plt.xlabel('주파수 (Hz)')
plt.ylabel('위상 (도)')
plt.grid(True, alpha=0.3)
plt.tight_layout()
plt.show()

슈미트 트리거 (Schmitt Trigger)

히스테리시스를 가진 비교기로 노이즈에 강합니다.

VH=+VsatR1R1+RfV_{H} = +V_{sat} \cdot \frac{R_1}{R_1 + R_f} VL=VsatR1R1+RfV_{L} = -V_{sat} \cdot \frac{R_1}{R_1 + R_f}


6. 전력 증폭기

급별 비교

도통각이론 효율특징
A급360도50%최고 선형성, 낮은 효율
B급180도78.5%교차 왜곡 발생
AB급180~360도50~78.5%B급 개선, 실용적
C급0~180도>78.5%고주파 RF 용도
D급스위칭~95%오디오/전원

푸시풀 증폭기 (AB급)

NPN과 PNP 트랜지스터 쌍을 사용해 교류 신호의 양방향을 각각 증폭합니다. 교차 왜곡 최소화를 위해 약 0.6~0.7 V의 바이어스 전압을 인가합니다.


7. 피드백 (Feedback)

부피드백의 장점

  1. 이득 안정화: 소자 변동에 둔감
  2. 대역폭 확장: BWclosed=BWopen×(1+Aβ)BW_{closed} = BW_{open} \times (1 + A\beta)
  3. 왜곡 감소: 비선형 왜곡을 (1+Aβ)(1 + A\beta)로 나눈 만큼 감소
  4. 임피던스 조정: 직렬 피드백→입력 임피던스 증가, 병렬 피드백→감소

안정성 분석

보드 선도에서 위상 여유(Phase Margin)와 이득 여유(Gain Margin)로 안정성을 판단합니다.

  • 위상 여유 PM > 45도: 안정
  • 이득 여유 GM > 6 dB: 안정

나이퀴스트 안정성 기준: 개루프 전달 함수의 나이퀴스트 선도가 (-1, j0) 점을 시계 방향으로 감싸지 않으면 안정합니다.


8. 능동 필터

버터워스 저역통과 필터

최대한 평탄한 통과대역 특성을 가집니다. n차 필터의 전달 함수 크기:

H(jω)=11+(ω/ωc)2n|H(j\omega)| = \frac{1}{\sqrt{1 + (\omega/\omega_c)^{2n}}}

Sallen-Key 2차 저역통과 필터

두 개의 저항, 두 개의 커패시터, Op-Amp 1개로 구성합니다.

H(s)=ω02s2+(ω0/Q)s+ω02H(s) = \frac{\omega_0^2}{s^2 + (\omega_0/Q)s + \omega_0^2}

품질 인자 QQ가 높을수록 공진 피크가 강해집니다. 버터워스 응답을 위해 Q=1/20.707Q = 1/\sqrt{2} \approx 0.707을 사용합니다.

import numpy as np
import matplotlib.pyplot as plt
from scipy import signal

# 버터워스 3차 저역통과 필터 (fc = 1kHz)
fc = 1000  # Hz
order = 3
b, a = signal.butter(order, 2*np.pi*fc, btype='low', analog=True)

f = np.logspace(1, 5, 1000)
w = 2 * np.pi * f
_, H = signal.freqs(b, a, worN=w)

plt.figure(figsize=(10, 5))
plt.subplot(1, 2, 1)
plt.semilogx(f, 20*np.log10(np.abs(H)), 'b-', linewidth=2)
plt.axvline(x=fc, color='r', linestyle='--', label='차단 주파수')
plt.xlabel('주파수 (Hz)')
plt.ylabel('이득 (dB)')
plt.title('버터워스 3차 LPF')
plt.legend()
plt.grid(True, alpha=0.3)

plt.subplot(1, 2, 2)
plt.semilogx(f, np.angle(H, deg=True), 'g-', linewidth=2)
plt.axvline(x=fc, color='r', linestyle='--', label='차단 주파수')
plt.xlabel('주파수 (Hz)')
plt.ylabel('위상 (도)')
plt.title('위상 응답')
plt.legend()
plt.grid(True, alpha=0.3)
plt.tight_layout()
plt.show()

9. 전원 공급 장치 회로

선형 레귤레이터

7805 계열: 고정 5V 출력. 드롭아웃 전압 약 2V.

Pdissipation=(VinVout)×IloadP_{dissipation} = (V_{in} - V_{out}) \times I_{load}

LM317 가변 레귤레이터:

Vout=1.25(1+R2R1)+IadjR2V_{out} = 1.25\left(1 + \frac{R_2}{R_1}\right) + I_{adj} \cdot R_2

스위칭 레귤레이터

Buck (강압형):

Vout=DVin,D=tonTV_{out} = D \cdot V_{in}, \quad D = \frac{t_{on}}{T}

Boost (승압형):

Vout=Vin1DV_{out} = \frac{V_{in}}{1-D}

Buck-Boost (반전형):

Vout=D1DVinV_{out} = -\frac{D}{1-D} V_{in}

스위칭 레귤레이터의 효율은 85~95%로 선형 레귤레이터보다 훨씬 높습니다.


10. 센서와 인터페이스 회로

온도 센서 인터페이스

NTC 서미스터 (부온도 계수): 온도 증가 시 저항 감소.

R(T)=R0eB(1/T1/T0)R(T) = R_0 \cdot e^{B(1/T - 1/T_0)}

계측 증폭기 (INA128 등):

Av=1+50 kΩRGA_v = 1 + \frac{50\text{ k}\Omega}{R_G}

높은 CMRR로 소신호 계측에 적합합니다.

ADC/DAC 인터페이스

ADC 핵심 파라미터:

  • 분해능 (Resolution): n비트 ADC는 2n2^n 레벨
  • SNR(dB) 6.02n+1.76\approx 6.02n + 1.76 (이상적 n비트 ADC)
  • 샘플링 주파수 2fmax\geq 2f_{max} (나이퀴스트 기준)

11. AI 하드웨어와 아날로그 회로

뉴로모픽 컴퓨팅의 아날로그 회로

딥러닝 추론을 하드웨어에서 효율적으로 수행하기 위해 아날로그 회로가 재조명받고 있습니다.

아날로그 곱셈-누산 (MAC) 연산: 가중치를 커패시터 전하나 전류 방향으로 표현하고, 옴의 법칙(I=GVI = GV)으로 곱셈을 수행합니다. 메모리 내 연산(Processing-In-Memory)의 핵심입니다.

Flash ADC 기반 AI 가속기: 고속 다비트 ADC로 활성화 함수 출력을 디지털 변환 후 다음 레이어에 전달합니다.

배터리 전원 AI 추론의 전력 관리

엣지 AI 기기에서 소비 전력 최소화:

  • 동적 전압/주파수 스케일링 (DVFS)
  • 전력 게이팅 (Power Gating)
  • 고효율 스위칭 레귤레이터 사용
  • 아날로그-디지털 혼합 신호 설계로 ADC 비트 수 최적화

12. 퀴즈

Q1. 다이오드의 쇼클리 방정식에서 열전압(Vt)의 값은 실온(25도)에서 얼마인가?

정답: 약 26 mV (정확히는 25.85 mV)

설명: 열전압은 VT=kT/qV_T = kT/q 로 계산됩니다. 볼츠만 상수 k=1.38×1023k = 1.38 \times 10^{-23} J/K, 절대온도 T=298T = 298 K (25도), 전자 전하 q=1.6×1019q = 1.6 \times 10^{-19} C를 대입하면 약 26 mV가 됩니다. 이 값은 다이오드의 지수적 I-V 특성 분석에 핵심입니다.

Q2. 연산증폭기에서 가상 단락(Virtual Short) 개념이란 무엇인가?

정답: 부피드백이 적용된 이상적 Op-Amp에서 반전 입력과 비반전 입력의 전압이 동일하다고 가정하는 개념입니다.

설명: 실제로 두 단자가 전기적으로 연결된 것은 아니지만, 높은 개루프 이득(보통 100,000배 이상)과 부피드백으로 인해 두 입력의 전압 차이가 거의 0이 됩니다. 이 개념을 이용하면 반전/비반전 증폭기의 이득을 간단하게 계산할 수 있습니다.

Q3. 공통 이미터 BJT 증폭기에서 이미터 저항(Re)를 바이패스 커패시터 없이 사용했을 때 어떤 효과가 있는가?

정답: 전압 이득이 감소하지만, 안정성(바이어스 안정화)이 향상되고 입력 임피던스가 증가합니다.

설명: 이미터 저항에 바이패스 커패시터가 없으면 소신호 이득 공식은 Av=RC/(re+RE)A_v = -R_C / (r_e + R_E) 가 됩니다. RER_E 항이 분모에 추가되어 이득이 줄지만, 온도나 소자 변화에 의한 이득 변동이 줄어들고 DC 바이어스가 안정화됩니다. 부피드백의 실제 적용 사례입니다.

Q4. Buck 컨버터에서 듀티 사이클이 0.4일 때 출력 전압은? (입력 12V)

정답: 4.8 V

설명: Buck 컨버터의 이상적 전압 변환 관계는 Vout=D×VinV_{out} = D \times V_{in} 입니다. 듀티 사이클 D = 0.4, 입력 전압 12 V를 대입하면 Vout=0.4×12=4.8V_{out} = 0.4 \times 12 = 4.8 V 가 됩니다. 듀티 사이클을 조절하여 출력 전압을 연속적으로 가변할 수 있는 것이 스위칭 레귤레이터의 장점입니다.

Q5. 버터워스 필터와 체비쇼프 필터의 차이점은?

정답: 버터워스 필터는 통과대역에서 최대 평탄 응답을 가지며, 체비쇼프 필터는 통과대역에서 리플을 허용하는 대신 더 가파른 롤오프 특성을 가집니다.

설명: 버터워스 필터는 통과대역 내 이득이 최대한 균일(Maximally Flat)하여 신호 왜곡이 적습니다. 체비쇼프 1형 필터는 통과대역 내 등리플(Equiripple) 특성을 가지며, 같은 차수에서 버터워스보다 훨씬 급격한 차단 특성을 보입니다. 응용에 따라 통과대역 평탄도와 롤오프 특성 간 트레이드오프를 선택해야 합니다.


참고 문헌

  • Sedra & Smith - Microelectronic Circuits, 8th Edition (Oxford University Press)
  • Razavi - Design of Analog CMOS Integrated Circuits, 2nd Edition (McGraw-Hill)
  • Texas Instruments - Op Amp Applications Handbook (Free PDF, ti.com)
  • Horowitz & Hill - The Art of Electronics, 3rd Edition (Cambridge University Press)
  • LTspice - 무료 SPICE 시뮬레이터 (Analog Devices 제공, analog.com/ltspice)
  • Falstad Circuit Simulator - 브라우저 기반 무료 회로 시뮬레이터 (falstad.com/circuit)

이 가이드는 전자회로 입문자부터 심화 학습자까지 활용할 수 있도록 설계되었습니다. SPICE 시뮬레이션과 Python 코드로 직접 회로를 검증해 보세요. Sedra & Smith 교재와 병행 학습하면 효과가 극대화됩니다.

Electronic Circuits Complete Guide: From Diodes to Op-Amps

Electronic Circuits Complete Guide: From Diodes to Op-Amps

Analog electronic circuits are at the heart of electrical engineering. This guide systematically covers circuit theory fundamentals, semiconductor devices, amplifier design, filters, and power supplies — all with practical examples and simulation code.


1. Circuit Theory Fundamentals

Kirchhoff's Laws

Kirchhoff's Voltage Law (KVL): The algebraic sum of all voltages around any closed loop is zero.

k=1nVk=0\sum_{k=1}^{n} V_k = 0

Kirchhoff's Current Law (KCL): The algebraic sum of all currents entering/leaving any node is zero.

k=1nIk=0\sum_{k=1}^{n} I_k = 0

import numpy as np

# Node voltage analysis using KCL
# Circuit: V1=12V, R1=1kOhm, R2=2kOhm, R3=3kOhm
# Conductance matrix (G) and current source vector (I)

G = np.array([
    [1/1e3 + 1/2e3, -1/2e3],
    [-1/2e3, 1/2e3 + 1/3e3]
])
I = np.array([12/1e3, 0])
V = np.linalg.solve(G, I)
print(f"Node voltages: V1={V[0]:.3f}V, V2={V[1]:.3f}V")

Thevenin and Norton Equivalent Circuits

Any linear circuit can be simplified into a Thevenin equivalent: a voltage source VthV_{th} in series with a resistance RthR_{th}. The Norton equivalent uses a current source IN=Vth/RthI_N = V_{th}/R_{th} in parallel with RN=RthR_N = R_{th}.

Maximum Power Transfer Theorem: Maximum power is delivered to a load when RL=RthR_L = R_{th}.

Pmax=Vth24RthP_{max} = \frac{V_{th}^2}{4R_{th}}

Superposition Principle

In a linear circuit with multiple independent sources, the response (voltage or current) at any element is the sum of responses due to each source acting alone (with all other sources replaced by their internal impedances).

AC Circuits and Phasor Analysis

Impedance representations:

  • Resistor: ZR=RZ_R = R
  • Inductor: ZL=jωLZ_L = j\omega L
  • Capacitor: ZC=1jωCZ_C = \frac{1}{j\omega C}

The transfer function H(jω)H(j\omega) and Bode plots are essential tools for frequency response analysis. The magnitude response in dB is HdB=20log10H|H|_{dB} = 20 \log_{10}|H|.


2. Diodes

Physics of the p-n Junction

When p-type semiconductor (majority carriers: holes) and n-type semiconductor (majority carriers: electrons) are joined, a depletion region forms at the junction. Under forward bias the depletion region narrows and current flows; under reverse bias the depletion region widens and current is blocked (except for a small reverse saturation current).

The built-in potential across the junction is typically 0.6–0.7 V for silicon at room temperature.

Shockley Diode Equation

ID=IS(eVD/nVT1)I_D = I_S\left(e^{V_D / nV_T} - 1\right)

where:

  • ISI_S: reverse saturation current (~101410^{-14} A for silicon)
  • nn: ideality factor (ideal: 1, practical: 1–2)
  • VT=kT/qV_T = kT/q: thermal voltage (~26 mV at 25°C)
import numpy as np
import matplotlib.pyplot as plt

# Diode I-V characteristic
V = np.linspace(-0.5, 0.8, 1000)
IS = 1e-14       # Reverse saturation current
n = 1.0          # Ideality factor
VT = 0.02585     # Thermal voltage at 25 degC

ID = IS * (np.exp(V / (n * VT)) - 1)
ID_clipped = np.clip(ID, -1e-12, 0.1)

plt.figure(figsize=(8, 5))
plt.plot(V, ID_clipped * 1000, 'b-', linewidth=2)
plt.axhline(y=0, color='k', linewidth=0.5)
plt.axvline(x=0, color='k', linewidth=0.5)
plt.xlabel('Diode Voltage V_D (V)')
plt.ylabel('Diode Current I_D (mA)')
plt.title('Diode I-V Characteristic Curve')
plt.grid(True, alpha=0.3)
plt.xlim(-0.5, 0.8)
plt.ylim(-0.01, 0.1)
plt.show()

Rectifier Circuits

Half-wave rectifier: One diode passes only the positive half cycle. Average output voltage Vavg=Vm/πV_{avg} = V_m / \pi.

Full-wave bridge rectifier: Four diodes conduct on both half cycles. Average output voltage Vavg=2Vm/πV_{avg} = 2V_m / \pi. The ripple frequency is twice the input frequency.

A smoothing capacitor reduces ripple voltage: VrippleILfCV_{ripple} \approx \frac{I_L}{f \cdot C}.

Zener Diode

Operates in reverse breakdown at a well-defined Zener voltage VZV_Z. Used as a simple voltage reference or clamp.

RS=VinVZIZ+ILR_S = \frac{V_{in} - V_Z}{I_Z + I_L}

Special Diodes

  • LED (Light-Emitting Diode): Emits photons during forward conduction. Forward voltage typically 1.8–3.5 V depending on material.
  • Photodiode: Generates current proportional to incident light; operated in reverse bias (photoconductive mode).
  • Schottky Diode: Metal-semiconductor junction; very low forward voltage (~0.3 V) and fast switching.

3. BJT Transistors

Structure and Operating Modes

The BJT (Bipolar Junction Transistor) has three terminals: Emitter (E), Base (B), and Collector (C).

Operating ModeB-E JunctionB-C JunctionApplication
CutoffReverseReverseSwitch OFF
ActiveForwardReverseAmplifier
SaturationForwardForwardSwitch ON

In the active region: IC=βIBI_C = \beta I_B, where β=hFE\beta = h_{FE} is the DC current gain (typically 50–300).

Also: IE=IB+IC=(β+1)IBI_E = I_B + I_C = (\beta + 1)I_B

DC Bias Design

The most stable bias configuration is the voltage divider bias:

VB=VCCR2R1+R2V_B = V_{CC} \cdot \frac{R_2}{R_1 + R_2} VE=VBVBEVB0.7 VV_E = V_B - V_{BE} \approx V_B - 0.7\text{ V} ICIE=VEREI_C \approx I_E = \frac{V_E}{R_E}

The stability factor S=1+RB/RES = 1 + R_B/R_E (where RB=R1R2R_B = R_1 \| R_2) determines how well the Q-point resists temperature-induced changes in β\beta.

Small-Signal Hybrid-Pi Model

Key parameters derived at the Q-point:

  • gm=IC/VTg_m = I_C / V_T: transconductance
  • rπ=β/gmr_\pi = \beta / g_m: input resistance (base to emitter, small signal)
  • ro=VA/ICr_o = V_A / I_C: output resistance (Early effect, VAV_A = Early voltage)

Amplifier Configuration Comparison

ConfigVoltage GainCurrent GainInput ZOutput ZUse Case
CEHigh (inverting)HighMediumMediumGeneral amplification
CC (Emitter Follower)~1HighHighLowBuffer, impedance matching
CBHigh~1LowHighHigh-frequency, RF

Common-emitter voltage gain (with bypass capacitor on RER_E):

Av=gm(RCro)RCreA_v = -g_m (R_C \| r_o) \approx -\frac{R_C}{r_e}

where re=VT/IC26 mV/ICr_e = V_T / I_C \approx 26\text{ mV} / I_C.


4. MOSFET

Device Physics and Operating Regions

The MOSFET (Metal-Oxide-Semiconductor FET) has four terminals: Gate (G), Drain (D), Source (S), and Body (B). For an n-channel NMOS device:

Cutoff region: VGS<VthV_{GS} < V_{th}ID0I_D \approx 0

Linear (Ohmic) region: VGS>VthV_{GS} > V_{th} and VDS<VGSVthV_{DS} < V_{GS} - V_{th}

ID=μnCoxWL[(VGSVth)VDSVDS22]I_D = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right]

Saturation region: VDSVGSVthV_{DS} \geq V_{GS} - V_{th}

ID=12μnCoxWL(VGSVth)2(1+λVDS)I_D = \frac{1}{2}\mu_n C_{ox} \frac{W}{L}(V_{GS} - V_{th})^2 (1 + \lambda V_{DS})

The parameter kn=μnCoxW/Lk_n = \mu_n C_{ox} W/L is the process transconductance parameter.

Small-Signal Parameters

At a given bias point:

  • gm=2μnCox(W/L)ID=2ID/(VGSVth)g_m = \sqrt{2\mu_n C_{ox}(W/L)I_D} = 2I_D/(V_{GS} - V_{th})
  • ro=1/(λID)r_o = 1/(\lambda I_D): output resistance from channel-length modulation

CMOS Inverter

The complementary MOSFET (CMOS) inverter pairs one PMOS and one NMOS transistor. During static operation, one transistor is always off, giving near-zero static power dissipation. This makes CMOS the dominant technology for digital logic.

Switching energy per transition: E=12CVDD2E = \frac{1}{2}CV_{DD}^2

MOSFET Current Mirrors

Used for biasing in analog ICs. A basic current mirror forces the output current to mirror the reference current, assuming matched devices. The Wilson and cascode mirrors improve output impedance.


5. Operational Amplifiers (Op-Amp)

Ideal Op-Amp Properties

ParameterIdeal ValueTypical Value (LM741)
Open-loop gain AOLA_{OL}Infinity~200,000
Input impedance RinR_{in}Infinity~2 MΩ
Output impedance RoutR_{out}0~75 Ω
BandwidthInfinity~1 MHz (GBW)
CMRRInfinity~90 dB
Slew rateInfinity0.5 V/µs

Virtual Short: With negative feedback, the differential input voltage V+VV^+ - V^- approaches zero because Vout=AOL(V+V)V_{out} = A_{OL}(V^+ - V^-) and any tiny differential drives the output to reduce the difference. Therefore V+VV^+ \approx V^-.

Virtual Open: Ideal input impedance is infinite, so no current flows into the input terminals.

Essential Op-Amp Circuits

Inverting amplifier:

Av=RfR1,Rin=R1A_v = -\frac{R_f}{R_1}, \quad R_{in} = R_1

Non-inverting amplifier:

Av=1+RfR1,RinA_v = 1 + \frac{R_f}{R_1}, \quad R_{in} \to \infty

Voltage follower (buffer):

Av=1,Rin,Rout0A_v = 1, \quad R_{in} \to \infty, \quad R_{out} \to 0

Differential amplifier (with matched resistors R1R_1 and RfR_f):

Vout=RfR1(V2V1)V_{out} = \frac{R_f}{R_1}(V_2 - V_1)

Summing amplifier:

Vout=(RfR1V1+RfR2V2+)V_{out} = -\left(\frac{R_f}{R_1}V_1 + \frac{R_f}{R_2}V_2 + \cdots\right)

Integrator (Miller integrator):

Vout(t)=1R1CVin(t)dtV_{out}(t) = -\frac{1}{R_1 C} \int V_{in}(t)\, dt

Differentiator:

Vout(t)=RfCdVindtV_{out}(t) = -R_f C \frac{dV_{in}}{dt}

import numpy as np
import matplotlib.pyplot as plt

# Inverting amplifier frequency response simulation
f = np.logspace(1, 7, 1000)   # 10 Hz to 10 MHz
GBW = 1e6                      # 1 MHz gain-bandwidth product
R1, Rf = 1e3, 10e3            # Resistor values

Av_ideal = -Rf / R1            # Ideal gain = -10

# Open-loop gain (first-order model)
A_open = GBW / (1j * f)

# Closed-loop gain
beta = R1 / (R1 + Rf)
Av_closed = A_open / (1 + A_open * beta)

plt.figure(figsize=(10, 6))
plt.subplot(2, 1, 1)
plt.semilogx(f, 20*np.log10(np.abs(Av_closed)), 'b-', linewidth=2, label='Actual gain')
plt.axhline(y=20*np.log10(abs(Av_ideal)), color='r', linestyle='--', label='Ideal gain (20 dB)')
plt.ylabel('Gain (dB)')
plt.title('Inverting Amplifier Frequency Response (GBW=1MHz, Av=-10)')
plt.legend()
plt.grid(True, alpha=0.3)

plt.subplot(2, 1, 2)
plt.semilogx(f, np.angle(Av_closed, deg=True), 'g-', linewidth=2)
plt.xlabel('Frequency (Hz)')
plt.ylabel('Phase (degrees)')
plt.grid(True, alpha=0.3)
plt.tight_layout()
plt.show()

Schmitt Trigger

A comparator with positive feedback, providing hysteresis to eliminate noise-induced false triggering.

VH=+VsatR1R1+Rf,VL=VsatR1R1+RfV_H = +V_{sat} \cdot \frac{R_1}{R_1 + R_f}, \quad V_L = -V_{sat} \cdot \frac{R_1}{R_1 + R_f}

The hysteresis window is ΔV=VHVL\Delta V = V_H - V_L.


6. Power Amplifiers

Class Comparison

ClassConduction AngleTheoretical EfficiencyCharacteristics
A360°50%Best linearity, low efficiency
B180°78.5%Crossover distortion
AB180°–360°50–78.5%Practical audio standard
C0°–180°>78.5%RF power amplifiers
DSwitching~95%Audio, power conversion

Push-Pull AB Class Amplifier

Pairs an NPN and PNP transistor to handle each half cycle. A bias voltage of 0.6–0.7 V applied between the bases eliminates the crossover distortion that plagues class B designs. The total harmonic distortion (THD) is significantly reduced compared to class B.

Class D Amplifier

Converts the input to a pulse-width modulated (PWM) signal using a comparator, switches power transistors, then reconstructs the audio with an LC low-pass filter. Efficiency exceeds 90%, making it ideal for battery-powered audio and motor drives.


7. Feedback

Benefits of Negative Feedback

  1. Gain stabilization: Closed-loop gain Af=A/(1+Aβ)1/βA_f = A/(1 + A\beta) \approx 1/\beta becomes independent of open-loop gain variations.
  2. Bandwidth extension: BWclosed=BWopen×(1+Aβ)BW_{closed} = BW_{open} \times (1 + A\beta)
  3. Distortion reduction: Nonlinear distortion is reduced by factor (1+Aβ)(1 + A\beta)
  4. Impedance modification: Series feedback increases input impedance; shunt feedback decreases it.

Stability Analysis

Phase Margin (PM) and Gain Margin (GM) from the Bode plot:

  • PM > 45°: Stable with good transient response (PM ~60° is typical target)
  • GM > 6 dB: Stable

The Nyquist stability criterion states that the closed-loop system is stable if the Nyquist plot of the open-loop transfer function L(jω)L(j\omega) does not encircle the point (1,j0)(-1, j0) clockwise.

Oscillators

When positive feedback is applied and the Barkhausen criterion is satisfied (Aβ=1|A\beta| = 1 and Aβ=0°\angle A\beta = 0° or 360°), the circuit oscillates.

  • Colpitts oscillator: Uses capacitive voltage divider in the feedback network.
  • Hartley oscillator: Uses inductive voltage divider.
  • Crystal oscillator: Exploits the piezoelectric resonance of a quartz crystal for high frequency stability.

8. Active Filters

Butterworth Low-Pass Filter

Provides the maximally flat magnitude response in the passband:

H(jω)=11+(ω/ωc)2n|H(j\omega)| = \frac{1}{\sqrt{1 + (\omega/\omega_c)^{2n}}}

The roll-off is 20n-20n dB/decade beyond the cutoff frequency ωc\omega_c.

Sallen-Key Second-Order Low-Pass Filter

A popular active filter topology using two R's, two C's, and one op-amp:

H(s)=ω02s2+(ω0/Q)s+ω02H(s) = \frac{\omega_0^2}{s^2 + (\omega_0/Q)s + \omega_0^2}

For a Butterworth response: Q=1/20.707Q = 1/\sqrt{2} \approx 0.707.

import numpy as np
import matplotlib.pyplot as plt
from scipy import signal

# 3rd-order Butterworth low-pass filter (fc = 1 kHz)
fc = 1000  # Hz
order = 3
b, a = signal.butter(order, 2*np.pi*fc, btype='low', analog=True)

f = np.logspace(1, 5, 1000)
w = 2 * np.pi * f
_, H = signal.freqs(b, a, worN=w)

plt.figure(figsize=(10, 5))
plt.subplot(1, 2, 1)
plt.semilogx(f, 20*np.log10(np.abs(H)), 'b-', linewidth=2)
plt.axvline(x=fc, color='r', linestyle='--', label='Cutoff frequency')
plt.xlabel('Frequency (Hz)')
plt.ylabel('Gain (dB)')
plt.title('3rd-Order Butterworth LPF')
plt.legend()
plt.grid(True, alpha=0.3)

plt.subplot(1, 2, 2)
plt.semilogx(f, np.angle(H, deg=True), 'g-', linewidth=2)
plt.axvline(x=fc, color='r', linestyle='--', label='Cutoff frequency')
plt.xlabel('Frequency (Hz)')
plt.ylabel('Phase (degrees)')
plt.title('Phase Response')
plt.legend()
plt.grid(True, alpha=0.3)
plt.tight_layout()
plt.show()

State Variable Filter

Implements low-pass, band-pass, and high-pass outputs simultaneously using three op-amps. Allows independent tuning of frequency and Q, making it ideal for parametric equalizers.


9. Power Supply Circuits

Linear Regulators

7805 fixed regulator: Output voltage 5 V, dropout voltage ~2 V, up to 1 A.

Pdissipation=(VinVout)×IloadP_{dissipation} = (V_{in} - V_{out}) \times I_{load}

Efficiency: η=Vout/Vin\eta = V_{out}/V_{in} — poor when the input-output differential is large.

LM317 adjustable regulator:

Vout=1.25(1+R2R1)+IadjR21.25(1+R2R1)V_{out} = 1.25\left(1 + \frac{R_2}{R_1}\right) + I_{adj} \cdot R_2 \approx 1.25\left(1 + \frac{R_2}{R_1}\right)

Switching Regulators

Buck converter (step-down):

Vout=DVin,D=tonTV_{out} = D \cdot V_{in}, \quad D = \frac{t_{on}}{T}

Boost converter (step-up):

Vout=Vin1DV_{out} = \frac{V_{in}}{1-D}

Buck-boost converter (inverting):

Vout=D1DVinV_{out} = -\frac{D}{1-D} V_{in}

Switching regulators achieve 85–95% efficiency because the switching transistor dissipates little power (it is either fully on or fully off). The trade-off is electromagnetic interference from switching noise.

Inductor selection: Lmin=(VinVout)DfsΔILL_{min} = \frac{(V_{in} - V_{out}) \cdot D}{f_s \cdot \Delta I_L}


10. Sensors and Interface Circuits

Temperature Sensor Interfaces

NTC thermistor (Negative Temperature Coefficient): Resistance decreases with temperature.

R(T)=R0eB(1/T1/T0)R(T) = R_0 \cdot e^{B(1/T - 1/T_0)}

A Wheatstone bridge linearizes the output; a difference amplifier amplifies the bridge imbalance voltage.

Thermocouple: Generates a small voltage (Seebeck effect, ~10–50 µV/°C). Requires a cold-junction compensation IC and an instrumentation amplifier.

Instrumentation Amplifier (INA128 etc.)

Av=1+50 kΩRGA_v = 1 + \frac{50\text{ k}\Omega}{R_G}

High CMRR (>100 dB) makes it ideal for measuring small differential signals in the presence of large common-mode noise (e.g., ECG, strain gauge, bridge sensors).

ADC/DAC Interface

Key ADC parameters:

  • Resolution: n-bit ADC quantizes into 2n2^n levels; LSB = VFS/2nV_{FS}/2^n
  • SNR: 6.02n+1.76\approx 6.02n + 1.76 dB (ideal n-bit ADC, full-scale sine wave)
  • Sampling rate: Must satisfy fs2fmaxf_s \geq 2f_{max} (Nyquist criterion)
  • Anti-aliasing filter: Low-pass filter before the ADC to remove frequencies above fs/2f_s/2

SPI and I2C are the dominant serial interfaces for ADC/DAC chips in embedded systems.


11. AI Hardware and Analog Circuits

Analog Computing for Neural Networks

Deep learning inference in hardware has revived interest in analog circuits for their energy efficiency.

Analog multiply-accumulate (MAC) unit: The core operation in neural network inference. Using Ohm's law (I=GVI = GV), conductance encodes a weight and voltage encodes an input — multiplication is performed physically. An array of such cells (crossbar array) performs a full matrix-vector multiply in a single step.

Processing-In-Memory (PIM): Flash, SRAM, or ReRAM cells store weights in-place and perform multiplication inside the memory array, eliminating the von Neumann bottleneck of moving data between memory and processor.

Mixed-Signal Design in AI Chips

Modern AI accelerators (e.g., Google TPU, Apple Neural Engine) blend digital MAC arrays with:

  • High-speed ADCs to convert analog outputs from crossbar arrays
  • DACs for weight update in on-chip training
  • Phase-locked loops (PLLs) for precise clock generation
  • Low-dropout (LDO) regulators for supply noise isolation

Power Management for Edge AI

Battery-powered edge inference demands aggressive power optimization:

  • DVFS (Dynamic Voltage and Frequency Scaling): Lower supply voltage reduces switching energy quadratically but also reduces speed.
  • Power gating: Completely shut down unused compute blocks between inference calls.
  • Quantization: Reducing weight precision from 32-bit float to 8-bit integer cuts memory bandwidth and power by 4×.
  • Analog sub-threshold circuits: Operating MOSFETs in weak inversion achieves nW-level power for always-on keyword detection.

12. Quiz

Q1. What is the thermal voltage (Vt) of a diode at room temperature (25°C)?

Answer: Approximately 26 mV (more precisely 25.85 mV).

Explanation: The thermal voltage is given by VT=kT/qV_T = kT/q. Substituting the Boltzmann constant k=1.38×1023k = 1.38 \times 10^{-23} J/K, absolute temperature T=298T = 298 K (25°C), and electron charge q=1.6×1019q = 1.6 \times 10^{-19} C gives approximately 26 mV. This value sets the scale of the exponential I-V characteristic and is fundamental to all small-signal diode and transistor analysis.

Q2. What is the "Virtual Short" concept in an op-amp circuit?

Answer: In an ideal op-amp with negative feedback, the voltages at the inverting and non-inverting input terminals are assumed to be equal.

Explanation: The two terminals are not physically shorted. However, because the open-loop gain is extremely large (often 100,000 or more), even a tiny differential input voltage would drive the output to the supply rail. Negative feedback continuously adjusts the output to keep the differential input near zero. This virtual short principle lets us easily analyze the gain of inverting and non-inverting amplifiers without solving complex circuit equations.

Q3. What happens when an emitter resistor (Re) is used in a common-emitter amplifier without a bypass capacitor?

Answer: The voltage gain decreases, but bias stability improves, input impedance increases, and distortion is reduced.

Explanation: Without a bypass capacitor, the small-signal gain becomes Av=RC/(re+RE)A_v = -R_C / (r_e + R_E). The extra RER_E in the denominator reduces the gain but introduces negative feedback that stabilizes the Q-point against temperature and device variation. The input impedance seen at the base becomes rπ+(β+1)REr_\pi + (\beta + 1)R_E, which can be much larger than rπr_\pi alone. This is a direct application of emitter degeneration (series-series negative feedback).

Q4. A Buck converter has a duty cycle of 0.4 and an input voltage of 12 V. What is the output voltage?

Answer: 4.8 V

Explanation: The ideal voltage conversion ratio of a Buck converter is Vout=D×VinV_{out} = D \times V_{in}. With D = 0.4 and VinV_{in} = 12 V: Vout=0.4×12=4.8V_{out} = 0.4 \times 12 = 4.8 V. The duty cycle is controlled by the PWM controller in a feedback loop to regulate the output against load and line variations. The inductor and output capacitor form a low-pass filter that smooths the switched waveform.

Q5. What is the key difference between a Butterworth filter and a Chebyshev filter?

Answer: A Butterworth filter has a maximally flat passband (no ripple), while a Chebyshev filter allows equiripple in the passband in exchange for a steeper roll-off.

Explanation: Butterworth filters are designed so that the magnitude response is as flat as possible in the passband, which minimizes signal distortion. Chebyshev Type I filters exhibit equal-magnitude ripple throughout the passband, but for the same filter order achieve a much sharper transition from passband to stopband. The choice depends on the application: audio and measurement systems favor Butterworth for flat amplitude response, while communications and anti-aliasing filters often use Chebyshev or elliptic designs for steeper roll-off with the same component count.


References

  • Sedra & SmithMicroelectronic Circuits, 8th Edition (Oxford University Press) — The definitive undergraduate textbook for analog electronics.
  • RazaviDesign of Analog CMOS Integrated Circuits, 2nd Edition (McGraw-Hill) — Essential for IC design.
  • Texas InstrumentsOp Amp Applications Handbook (Free PDF at ti.com) — Comprehensive practical Op-Amp design reference.
  • Horowitz & HillThe Art of Electronics, 3rd Edition (Cambridge University Press) — Practical circuits bible.
  • LTspice — Free SPICE simulator from Analog Devices (analog.com/ltspice) — Industry-standard tool for analog circuit simulation.
  • Falstad Circuit Simulator — Browser-based free circuit simulator (falstad.com/circuit) — Great for quick visualization.

This guide covers the core topics of analog electronics as taught in a typical first or second-year electrical engineering curriculum. Work through the Python simulations, use LTspice to verify your designs, and pair this guide with Sedra & Smith for rigorous mathematical treatment.