Computer Architecture Complete Guide: From ISA to GPU Parallel Architecture

Application Software
       ↓
Operating System
       ↓
ISA (Instruction Set Architecture)  ← Hardware/Software boundary
       ↓
Microarchitecture
       ↓
Logic Gates
       ↓
Transistors

CPU Time = Instruction Count × CPI × Clock Cycle Time
         = Instruction Count × CPI / Clock Rate

Speedup = 1 / ((1 - f) + f/s)

R-type (Register operations):
[funct7 | rs2 | rs1 | funct3 | rd | opcode]
  7-bit   5-bit 5-bit  3-bit  5-bit  7-bit

I-type (Immediate / Load):
[imm[11:0] | rs1 | funct3 | rd | opcode]
  12-bit    5-bit   3-bit  5-bit  7-bit

S-type (Store):
[imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode]

B-type (Branch):
[imm[12|10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode]

U-type (Upper immediate):
[imm[31:12] | rd | opcode]

J-type (JAL):
[imm[20|10:1|11|19:12] | rd | opcode]

# RISC-V Assembly Examples
# Basic arithmetic
add  a0, a0, a1      # a0 = a0 + a1
sub  t0, t1, t2      # t0 = t1 - t2
addi t0, t0, 10      # t0 = t0 + 10 (immediate)
mul  a0, a1, a2      # a0 = a1 * a2

# Memory access (Load/Store)
lw   t0, 0(a0)       # t0 = Memory[a0 + 0]  (word load)
lh   t1, 2(a0)       # t1 = Memory[a0 + 2]  (halfword load)
lb   t2, 1(a0)       # t2 = Memory[a0 + 1]  (byte load)
sw   t0, 4(a0)       # Memory[a0 + 4] = t0  (word store)

# Logical operations
and  t0, t1, t2      # t0 = t1 & t2
or   t0, t1, t2      # t0 = t1 | t2
xor  t0, t1, t2      # t0 = t1 ^ t2
sll  t0, t1, t2      # t0 = t1 << t2 (logical left shift)
srl  t0, t1, t2      # t0 = t1 >> t2 (logical right shift)

# Branches and jumps
beq  t0, t1, label   # if t0 == t1, jump to label
bne  t0, t1, label   # if t0 != t1, jump to label
blt  t0, t1, label   # if t0 < t1,  jump to label
bge  t0, t1, label   # if t0 >= t1, jump to label
jal  ra, func        # ra = PC+4; jump to func
jalr ra, 0(t0)       # ra = PC+4; jump to address in t0

# RISC-V Register Conventions
# x0  (zero): hardwired zero
# x1  (ra):   return address
# x2  (sp):   stack pointer
# x10-x17 (a0-a7): function arguments / return values
# x5-x7, x28-x31 (t0-t6): temporaries
# x8-x9, x18-x27 (s0-s11): saved registers

// C code
int factorial(int n) {
    if (n <= 1) return 1;
    return n * factorial(n - 1);
}

# RISC-V Assembly (recursive factorial)
factorial:
    addi sp, sp, -16     # Allocate stack frame
    sw   ra, 12(sp)      # Save return address
    sw   a0, 8(sp)       # Save n

    addi t0, zero, 1
    bgt  a0, t0, recurse # if n > 1, recurse
    addi a0, zero, 1     # return 1
    j    done

recurse:
    addi a0, a0, -1      # n - 1
    jal  ra, factorial   # recursive call
    lw   t0, 8(sp)       # restore n
    mul  a0, t0, a0      # n * factorial(n-1)

done:
    lw   ra, 12(sp)      # restore return address
    addi sp, sp, 16      # free stack frame
    jalr zero, 0(ra)     # return

ADD:  result = A + B
SUB:  result = A + (~B + 1) = A - B  (two's complement)
AND:  result = A AND B
OR:   result = A OR B
XOR:  result = A XOR B
SLT:  result = (A < B) ? 1 : 0  (Set Less Than)
SLL:  result = A << B

FA0: S0 = A0 XOR B0 XOR Cin;  C1 = carry out
FA1: S1 = A1 XOR B1 XOR C1;  C2 = carry out
...

Gi = Ai AND Bi       (carry generate)
Pi = Ai XOR Bi       (carry propagate)
Ci+1 = Gi OR (Pi AND Ci)

Instruction flow (R-type ADD):
1. IF:  PC → instruction memory → fetch instruction
2. ID:  Read rs1, rs2 from register file; generate control signals
3. EX:  ALU computes rs1 + rs2
4. MEM: (R-type has no memory access)
5. WB:  Write ALU result to rd

Stage  Abbr  Function
------+------+--------------------------------------------
Fetch  IF    Fetch instruction from memory using PC
Decode ID    Decode instruction, read registers, gen control
Execute EX   Perform ALU operation
Memory MEM   Read/write data memory
Writeback WB Write result back to register file

Cycle:  1    2    3    4    5    6    7    8
Inst 1: IF   ID   EX  MEM   WB
Inst 2:      IF   ID   EX  MEM   WB
Inst 3:           IF   ID   EX  MEM   WB
Inst 4:                IF   ID   EX  MEM   WB

add t0, t1, t2    # write t0 (WB: cycle 5)
sub t3, t0, t4    # read t0  (ID: cycle 3) → RAW hazard!

# Load-use hazard: 1 stall cycle unavoidable
lw  t0, 0(a0)      # load from memory
add t1, t0, t2     # use t0 immediately → MEM→EX forwarding impossible
# Solution: compiler inserts an independent instruction
lw  t0, 0(a0)
add t3, t4, t5     # independent instruction fills the slot
add t1, t0, t2     # t0 is now ready

beq t0, t1, label  # branch decision made in EX stage
# Instructions already fetched in IF/ID may be wrong

Intel Core: 6-way out-of-order execution (OoO)
AMD Zen 4:  4-way decode + OoO execution
ARM Cortex-X4: 5-way decode

Registers
  Size: ~1KB  |  Latency: 1 cycle       |  Cost: very high

L1 Cache (on-chip)
  Size: 32-64KB  |  Latency: 4-5 cycles  |  Cost: high

L2 Cache (on-chip)
  Size: 256KB-1MB  |  Latency: 12-15 cycles  |  Cost: medium

L3 Cache (on-chip, shared)
  Size: 8-64MB  |  Latency: 30-40 cycles  |  Cost: low

DRAM (Main Memory)
  Size: 8-256GB  |  Latency: 200-300 cycles  |  Cost: very low

SSD / NVMe
  Size: 1-4TB  |  Latency: 10,000+ cycles  |  Cost: extremely low

// Spatial locality optimization
// Bad: column-major access (frequent cache misses)
for (int j = 0; j < N; j++)
    for (int i = 0; i < N; i++)
        sum += A[i][j];  // A[0][0], A[1][0], A[2][0]... (non-contiguous)

// Good: row-major access (cache-friendly)
for (int i = 0; i < N; i++)
    for (int j = 0; j < N; j++)
        sum += A[i][j];  // A[0][0], A[0][1], A[0][2]... (contiguous memory)

[Tag (20 bits) | Index (6 bits) | Offset (6 bits)]

Virtual Address (VA): Address used by the process (0x0000 to 0xFFFFFFFF)
Physical Address (PA): Actual DRAM address
Page: Fixed-size block of virtual/physical memory (typically 4KB)

Virtual Address [VPN | Page Offset]
                    ↓
             Page table lookup
                    ↓
Physical Address [PFN | Page Offset]

[PML4 (9 bits) | PDPT (9 bits) | PD (9 bits) | PT (9 bits) | Offset (12 bits)]

TLB Hit:  VA → TLB lookup → PA  (1-2 cycles)
TLB Miss: VA → page table walk → PA  (100+ cycles)

PCIe 5.0:   x16 = 128 GB/s bidirectional
NVMe (PCIe): up to 7 GB/s sequential read (Gen4)
USB 4.0:    up to 40 Gbps
DDR5-6400:  51.2 GB/s per channel

Modified (M):  This core holds the only (modified) copy
Exclusive (E): This core holds the only copy, matches memory
Shared (S):    Multiple cores hold read-only copies
Invalid (I):   This copy is stale (another core modified it)

#include <omp.h>
#include <stdio.h>
#include <stdlib.h>

// Parallel array summation
int main() {
    int n = 1000000;
    long long sum = 0;
    int *arr = malloc(n * sizeof(int));

    for (int i = 0; i < n; i++)
        arr[i] = i + 1;

    // Reduction clause ensures thread-safe accumulation
    #pragma omp parallel for reduction(+:sum) schedule(static)
    for (int i = 0; i < n; i++) {
        sum += arr[i];
    }

    printf("Sum = %lld\n", sum);  // Expected: 500000500000

    // Print thread IDs
    #pragma omp parallel
    {
        int tid = omp_get_thread_num();
        int nthreads = omp_get_num_threads();
        printf("Thread %d of %d\n", tid, nthreads);
    }

    free(arr);
    return 0;
}

// Cache-friendly parallel matrix multiplication
void matmul(float *A, float *B, float *C, int N) {
    #pragma omp parallel for collapse(2) schedule(dynamic, 64)
    for (int i = 0; i < N; i++) {
        for (int j = 0; j < N; j++) {
            float sum = 0.0f;
            for (int k = 0; k < N; k++) {
                sum += A[i*N + k] * B[k*N + j];
            }
            C[i*N + j] = sum;
        }
    }
}

Socket 0 (Core 0-15)  ←→ Local DRAM (64GB)  [~80ns]
      ↕ QPI / Infinity Fabric
Socket 1 (Core 16-31) ←→ Local DRAM (64GB)  [~80ns]

Socket 0 accessing Socket 1 memory: ~160ns (2x latency)

Warp: 32 threads executing the same instruction (NVIDIA)
→ All 32 threads execute the same instruction simultaneously
→ Each thread operates on different data

Warp scheduler: On memory stall, immediately switch to another warp
→ Thousands of warps rotate rapidly, hiding memory latency

GPU
├── GPC (Graphics Processing Cluster) x 8
│   └── SM (Streaming Multiprocessor) x 7-12
│       ├── CUDA Core x 128 (FP32 operations)
│       ├── Tensor Core x 4 (matrix multiply, AI)
│       ├── RT Core x 1 (ray tracing)
│       ├── Warp Scheduler x 4
│       ├── Register File (256KB)
│       └── Shared Memory / L1 Cache (128-256KB)
└── L2 Cache (shared, tens of MB)

#include <cuda_runtime.h>
#include <stdio.h>

// GPU kernel: vector addition
__global__ void vectorAdd(float *a, float *b, float *c, int n) {
    // Global thread index
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < n) {
        c[idx] = a[idx] + b[idx];
    }
}

int main() {
    int n = 1 << 20;  // 1M elements
    size_t size = n * sizeof(float);

    // Host (CPU) memory
    float *h_a = (float*)malloc(size);
    float *h_b = (float*)malloc(size);
    float *h_c = (float*)malloc(size);

    // Device (GPU) memory
    float *d_a, *d_b, *d_c;
    cudaMalloc(&d_a, size);
    cudaMalloc(&d_b, size);
    cudaMalloc(&d_c, size);

    // Host → Device transfer
    cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);

    // Launch kernel: 256 threads per block
    int threadsPerBlock = 256;
    int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
    vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_a, d_b, d_c, n);

    // Device → Host transfer
    cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);

    cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
    free(h_a); free(h_b); free(h_c);
    return 0;
}

// Tiled matrix multiplication using shared memory
#define TILE_SIZE 16

__global__ void matmulShared(float *A, float *B, float *C, int N) {
    __shared__ float tileA[TILE_SIZE][TILE_SIZE];
    __shared__ float tileB[TILE_SIZE][TILE_SIZE];

    int row = blockIdx.y * TILE_SIZE + threadIdx.y;
    int col = blockIdx.x * TILE_SIZE + threadIdx.x;
    float sum = 0.0f;

    for (int t = 0; t < N / TILE_SIZE; t++) {
        // Load tiles into shared memory
        tileA[threadIdx.y][threadIdx.x] = A[row * N + t * TILE_SIZE + threadIdx.x];
        tileB[threadIdx.y][threadIdx.x] = B[(t * TILE_SIZE + threadIdx.y) * N + col];
        __syncthreads();  // Wait for all threads to finish loading

        for (int k = 0; k < TILE_SIZE; k++)
            sum += tileA[threadIdx.y][k] * tileB[k][threadIdx.x];
        __syncthreads();
    }

    if (row < N && col < N)
        C[row * N + col] = sum;
}

Regular CUDA Core: 1 FP32 MAC per cycle
4th-gen Tensor Core: 16x16x16 matrix multiply = 4096 FP16 MACs per cycle

HBM3E (2024): 9.6 Gbps/pin, 8-stack = 1.2 TB/s per package
GDDR6X (RTX 4090): 21 Gbps/pin, 384-bit = 1 TB/s
DDR5-6400: 51.2 GB/s per channel (CPU)

#include <stdlib.h>

#define N 4096

float A[N][N], B[N][N], C[N][N];

// Inefficient: column-major traversal (many cache misses)
void matmul_naive() {
    for (int i = 0; i < N; i++)
        for (int j = 0; j < N; j++)
            for (int k = 0; k < N; k++)
                C[i][j] += A[i][k] * B[k][j];  // B[k][j] strides across rows
}

// Efficient: loop tiling (reuses cache blocks)
#define BLOCK 64
void matmul_tiled() {
    for (int ii = 0; ii < N; ii += BLOCK)
        for (int jj = 0; jj < N; jj += BLOCK)
            for (int kk = 0; kk < N; kk += BLOCK)
                for (int i = ii; i < ii+BLOCK && i < N; i++)
                    for (int j = jj; j < jj+BLOCK && j < N; j++)
                        for (int k = kk; k < kk+BLOCK && k < N; k++)
                            C[i][j] += A[i][k] * B[k][j];
}

#include <immintrin.h>  // AVX2 intrinsics

// Process 8 floats simultaneously with AVX2
void vector_add_avx2(float *a, float *b, float *c, int n) {
    int i;
    for (i = 0; i <= n - 8; i += 8) {
        __m256 va = _mm256_loadu_ps(&a[i]);   // Load 8 floats
        __m256 vb = _mm256_loadu_ps(&b[i]);
        __m256 vc = _mm256_add_ps(va, vb);    // Add 8 floats at once
        _mm256_storeu_ps(&c[i], vc);          // Store 8 floats
    }
    // Handle remaining elements
    for (; i < n; i++)
        c[i] = a[i] + b[i];
}